米6体育平台手机版

ZHCSES1B March 2016 – October 2018 ADS1282-SP

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机械数据 (封装 | 引脚)

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7.5 Electrical Characteristics

AVDD = 2.5 V, AVSS = –2.5 V, ƒ_CLK⁽¹⁾ = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒ_DATA = 1000 SPS, over operating temperature range, unless otherwise noted. Typical values are T_J = 25°C. A total ionizing dose of 50 kRad (Si) exposure at a low dose rate of < 10 mRads (Si)/s, post tested at 25°C.

PARAMETER		TEST CONDITIONS		5962L1423101VXC			5962L1423102VXC			UNIT
PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Full-scale input voltage	V_IN = (AINP – AINN)		(VREFP – VREFN) / (PGA)			(VREFP – VREFN) / (PGA)			Vpp-diff
AINP or AINN	Absolute input range			AVSS + 0.7		AVDD – 1.25	AVSS + 0.7		AVDD – 1.25	V
	PGA input voltage noise density				5			5		nV/√Hz
	Differential input impedance⁽²⁾				1			1		GΩ
	Common-mode input impedance				100			100		MΩ
	Input bias current				1			1		nA
	Crosstalk	ƒ = 31.25 Hz			–128			–128		dB
	MUX on-resistance				30			30		Ω
PGA OUTPUT (CAPP, CAPN)
	Absolute output range			AVSS + 0.4		AVDD – 0.4	AVSS + 0.4		AVDD – 0.4	V
	PGA differential output impedance				600			600		Ω
	Output impedance tolerance				±10%			±10%
	External bypass capacitance				10	100		10	100	nF
	Modulator differential input impedance				55			55		kΩ
AC PERFORMANCE
SNR	Signal-to-noise ratio⁽³⁾			112	124		112	124		dB
THD	Total harmonic distortion⁽⁴⁾	PGA = 1...16			–122	–99		–122	–101	dB
		PGA = 32			–117	–90		–117	–92
		PGA = 64			–115			–115
SFDR	Spurious-free dynamic range				123			123		dB
DC PERFORMANCE
	Resolution	No missing codes		31			31			bits
ƒ_DATA	Data rate	FIR filter mode		250		4000	250		4000	SPS
ƒ_DATA	Data rate	SINC filter mode		8000		128000	8000		128000	SPS
	Integral nonlinearity (INL)⁽⁵⁾	Differential input			0.00005	0.0090		0.00005	0.0090	% FSR⁽⁶⁾
	Integral nonlinearity (INL)⁽⁵⁾	Differential input	Offset error			0.0170			0.0170	% FSR⁽⁶⁾
	Offset error after calibration⁽⁷⁾	Shorted input			50	200		50	200	μV
	Offset error after calibration⁽⁷⁾		Offset drift			750			750	μV
	Gain error⁽⁸⁾				1			1		μV
	Gain error after calibration⁽⁷⁾				0.02			0.02		μV/°C
	Gain drift			–1.5%	–1.0%	–0.5%	–1.5%	–1.0%	–0.5%
	Gain matching⁽¹²⁾				0.0002%			0.0002%
	Common-mode rejection	PGA = 1			2			2		ppm/°C
	Common-mode rejection	PGA = 16			9			9		ppm/°C
					0.3%	0.8%		0.3%	0.8%
		ƒ_CM = 60 Hz⁽⁹⁾		82	110		82	110		dB
AVDD, AVSS	Power-supply rejection	ƒ_PS = 60 Hz⁽⁹⁾		80	90		80	90		dB
AVDD, AVSS			Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾	64	90		64	90		dB
DVDD				90	115		90	115		dB
VOLTAGE REFERENCE INPUTS
	Reference input voltage	(V_REF = VREFP – VREFN)		0.5	5	(AVDD – AVSS) + 0.2	0.5	5	(AVDD – AVSS) + 0.2	V
VREFN	Negative reference input			AVSS – 0.1		VREFP – 0.5	AVSS – 0.1		VREFP – 0.5	V
VREFP	Positive reference input			VREFN + 0.5		AVDD + 0.1	VREFN + 0.5		AVDD + 0.1	V
	Reference input impedance				85			85		kΩ
DIGITAL FILTER RESPONSE
	Passband ripple					±0.003			±0.003	dB
	Passband (–0.01 dB)				0.375 × ƒ_DATA			0.375 × ƒ_DATA		Hz
	Bandwidth (–3 dB)				0.413 × ƒ_DATA			0.413 × ƒ_DATA		Hz
	High-pass filter corner			0.1		10	0.1		10	Hz
	Stop band attenuation⁽¹⁰⁾			135			135			dB
	Stop band				0.500 × ƒ_DATA			0.500 × ƒ_DATA		Hz
	Group delay	Minimum phase filter⁽¹³⁾			5 / ƒ_DATA			5 / ƒ_DATA		s
	Group delay	Settling time (latency)			31 / ƒ_DATA			31 / ƒ_DATA		s
		Minimum phase filter			62 / ƒ_DATA			62 / ƒ_DATA		s
		Linear phase filter			62 / ƒ_DATA			62 / ƒ_DATA		s
DIGITAL INPUT/OUTPUT
V_IH				0.8 × DVDD		DVDD	0.8 × DVDD		DVDD	V
V_IL				DGND		0.2 × DVDD	DGND		0.2 × DVDD	V
V_OH		I_OH = 1 mA		0.8 × DVDD			0.8 × DVDD			V
V_OL		I_OL = 1 mA				0.2 × DVDD			0.2 × DVDD	V
	Input leakage	0 < V_{DIGITAL IN} < DVDD				±10			±10	μA
ƒ_CLK	Clock input			1		4.096	1		4.096	MHz
ƒ_SCLK	Serial clock rate					ƒ_CLK / 2			ƒ_CLK / 2	MHz
POWER SUPPLY
AVSS				–2.6		0	–2.6		0	V
AVDD				AVSS + 4.75		AVSS + 5.25	AVSS + 4.75		AVSS + 5.25	V
DVDD				1.75		3.6	1.75		3.6	V
	AVDD, AVSS current	High-resolution mode			4.5	7.2		4.5	6.5	\|mA\|
		High-resolution mode	Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾			11			11	\|mA\|
		Power-down mode			–200	200		-200	200	\|μA\|
		Power-down mode	Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾			5			5	\|mA\|
		Standby mode			–200	200		-200	200	\|μA\|
		Standby mode	Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾			5			5	\|mA\|
	DVDD current	High-resolution mode			0.6	1.5		0.6	1.2	mA
		Power-down mode⁽¹¹⁾			32	120		32	120	μA
		Standby mode			73	175		73	175	μA
	Power dissipation	High-resolution mode			25	41		25	41	mW
		High-resolution mode	Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾			60			60	mW
		Power-down mode			0.45	0.95		0.45	0.95	mW
		Power-down mode	Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾			25.4			25.4	mW
		Standby mode			0.58	1.1		0.58	1.1	mW
		Standby mode	Post 50 kRads (Si), T_J = 25°C⁽¹⁴⁾			25.4			25.4	mW

(1) ƒ_CLK = system clock.

(2) Input impedance is improved by disabling input chopping (CHOP bit = 0).

(3) V_IN = 20 mV_DC / PGA, see Table 1.

(4) V_IN = 31.25 Hz, –0.5 dBFS.

(5) Best-fit method.

(6) FSR: Full-scale range = ±V_REF / (2 × PGA).

(7) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).

(8) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.

(9) ƒ_CM is the input common-mode frequency. ƒ_PS is the power-supply frequency.

(10) Input frequencies in the range of Nƒ_CLK / 512 ± ƒ_DATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120 dB, typ.

(11) CLK input stopped.

(12) Gain match relative to PGA = 1.

(13) At DC. See Figure 42.

(14) The maximum limit applies to SMD 5962L14231 post 50 kRads (Si) test at 25°C.