8.3.17 Continuous-Sync Mode

In Continuous-sync mode, either a single sync pulse or a continuous clock may be applied. When a single sync pulse is applied (rising edge), the device behaves similar to the Pulse-sync mode. However, in this mode, DRDY continues to toggle unaffected but the DOUT output is held low until data are ready, 63 DRDY periods later. When the conversion data are non-zero, new conversion data are ready (as shown in Figure 46).

When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data rate or the device re-synchronizes. Synchronization results in the restarting of the digital filter and an interruption of 63 readings (refer to Pulse-Sync Timing Requirements).

When the sync input is first applied, the device re-synchronizes (under the condition t_SYNC ≠ N / ƒ_DATA). DRDY continues to output but DOUT is held low until the new data are ready. Then, if SYNC is applied again and the period matches an integral multiple of the output data rate, the device freely runs without re-synchronization. The phase of the applied clock and output data rate (DRDY) are not matched because of the initial delay of DRDY after SYNC is first applied. Figure 47 shows the timing for Continuous-Sync mode.

A SYNC clock input should be applied after the Continuous-Sync mode is set. The first rising edge of SYNC then causes a synchronization.

Figure 46. Pulse-Sync Timing, Continuous-Sync Timing With Single Sync

Figure 47. Continuous-Sync Timing With Sync Clock