米6体育平台手机版

ZHCSES1B March 2016 – October 2018 ADS1282-SP

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8.4.1 Modulator Output Mode

The modulator digital stream output is accessible directly, bypassing and disabling the internal digital filter. The modulator output mode is activated by setting the CONFIG0 register bits FILTR[1:0] = 00. Pins M0 and M1 then become the modulator data outputs and the MCLK becomes the modulator clock output. When not in the modulator mode, these pins are inputs and must be tied.

The modulator output is composed of three signals: one output for the modulator clock (MCLK) and two outputs for the modulator data (M0 and M1). The modulator clock output rate is ƒ_MOD (ƒ_CLK / 4). The SYNC input resets the MCLK phase, as shown in Figure 56. The SYNC input is latched on the rising edge of CLK. The MCLK resets and the next rising edge of MCLK occurs five CLK periods later.

The modulator output data are two bits wide, which must be merged together before being filtered. Use the time domain equation of Equation 5 to merge the data outputs.

NOINDENT:

MCLK = ƒ_CLK / 4.

Figure 56. Modulator Mode Timing

Table 10. Modulator Output Timing for Figure 56

PARAMETER		MIN	TYP	MAX	UNIT
t_MCD0, 1	MCLK rising edge to M0, M1 valid propagation delay			100	ns
t_CMD	CLK rising edge (after SYNC rising edge) to MCLK rising edge CMD		5		1/ƒ_CLK
t_CSHD	CLK to SYNC hold time to not latch on CLK edge	10			ns
t_SCSU	SYNC to CLK setup time to latch on CLK edge	10			ns
t_SYMD	SYNC to stable bit stream			16	1/ƒ_MOD