ZHCSIU4A September 2018 – August 2019 ADS1284
PRODUCTION DATA.
Figure 82 shows the digital connection to a controller (field programmable gate array or microcontroller). In this example, two ADCs are shown connected to one controller. The ADCs share the same serial interface (SCLK, DIN, and DOUT). The ADC is selected for communication by strobing each CS low. The DRDY output from both ADCs can be used; however, when the devices are synchronized, the DRDY output from only one device is sufficient.
The modulator overrange flag (MFLAG) from each device ties to the controller input. For synchronization, connect all ADCs to the same SYNC signal. For reset, either connect all ADCs to the same RESET signal or connect the ADCs to individual RESET signals.
Avoid ringing on the digital inputs to the ADCs. Place 47-Ω resistors in series with the digital traces to help reduce ringing by controlling impedances. Place the resistors at the source (driver) end of the trace. Do not float unused digital inputs; tie them to DVDD or GND.