ZHCSIU4A September   2018  – August 2019 ADS1284

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs and Multiplexer
      2. 8.3.2 Programmable Gain Amplifier (PGA)
      3. 8.3.3 Analog-to-Digital Converter (ADC)
        1. 8.3.3.1 Modulator
          1. 8.3.3.1.1 Modulator Overrange
          2. 8.3.3.1.2 Modulator Input Impedance
          3. 8.3.3.1.3 Modulator Overrange Detection (MFLAG)
          4. 8.3.3.1.4 Offset
          5. 8.3.3.1.5 Voltage Reference Inputs (VREFP, VREFN)
        2. 8.3.3.2 Digital Filter
          1. 8.3.3.2.1 Sinc Filter Section (sinx / x)
          2. 8.3.3.2.2 FIR Section
          3. 8.3.3.2.3 Group Delay and Step Response
            1. 8.3.3.2.3.1 Linear Phase Response
            2. 8.3.3.2.3.2 Minimum Phase Response
          4. 8.3.3.2.4 HPF Section
    4. 8.4 Device Functional Modes
      1. 8.4.1  Synchronization (SYNC PIN and SYNC Command)
        1. 8.4.1.1 Pulse-Sync Mode
        2. 8.4.1.2 Continuous-Sync Mode
      2. 8.4.2  Reset (RESET Pin and Reset Command)
      3. 8.4.3  Master Clock Input (CLK)
      4. 8.4.4  Power-Down (PWDN Pin and STANDBY Command)
      5. 8.4.5  Power-On Sequence
      6. 8.4.6  DVDD Power Supply
      7. 8.4.7  Serial Interface
        1. 8.4.7.1 Chip Select (CS)
        2. 8.4.7.2 Serial Clock (SCLK)
        3. 8.4.7.3 Data Input (DIN)
        4. 8.4.7.4 Data Output (DOUT)
        5. 8.4.7.5 Serial Port Auto Timeout
        6. 8.4.7.6 Data Ready (DRDY)
      8. 8.4.8  Data Format
      9. 8.4.9  Reading Data
        1. 8.4.9.1 Read-Data-Continuous Mode
        2. 8.4.9.2 Read-Data-By-Command Mode
      10. 8.4.10 One-Shot Operation
      11. 8.4.11 Offset and Full-Scale Calibration Registers
        1. 8.4.11.1 OFC[2:0] Registers
        2. 8.4.11.2 FSC[2:0] Registers
      12. 8.4.12 Calibration Commands (OFSCAL and GANCAL)
        1. 8.4.12.1 OFSCAL Command
        2. 8.4.12.2 GANCAL Command
      13. 8.4.13 User Calibration
    5. 8.5 Programming
      1. 8.5.1 Commands
        1. 8.5.1.1  SDATAC Requirements
        2. 8.5.1.2  WAKEUP: Wake-Up From Standby Mode
        3. 8.5.1.3  STANDBY: Standby Mode
        4. 8.5.1.4  SYNC: Synchronize the Analog-to-Digital Conversion
        5. 8.5.1.5  RESET: Reset the Device
        6. 8.5.1.6  RDATAC: Read Data Continuous
        7. 8.5.1.7  SDATAC: Stop Read Data Continuous
        8. 8.5.1.8  RDATA: Read Data by Command
        9. 8.5.1.9  RREG: Read Register Data
        10. 8.5.1.10 WREG: Write to Register
        11. 8.5.1.11 OFSCAL: Offset Calibration
        12. 8.5.1.12 GANCAL: Gain Calibration
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
        4. 8.6.1.4 HPF0 and HPF1 Registers
          1. 8.6.1.4.1 HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]
          2. 8.6.1.4.2 HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]
        5. 8.6.1.5 OFC0, OFC1, OFC2 Registers
          1. 8.6.1.5.1 OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]
          2. 8.6.1.5.2 OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]
          3. 8.6.1.5.3 OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]
        6. 8.6.1.6 FSC0, FSC1, FSC2 Registers
          1. 8.6.1.6.1 FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]
          2. 8.6.1.6.2 FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]
          3. 8.6.1.6.3 FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Geophone Interface
      2. 9.2.2 Digital Interface
    3. 9.3 Initialization Set Up
  10. 10器件和文档支持
    1. 10.1 接收文档更新通知
    2. 10.2 社区资源
    3. 10.3 商标
    4. 10.4 静电放电警告
    5. 10.5 Glossary
  11. 11机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, fCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, High-Resolution and Low-Power modes, Offset enabled (75 mV), Chop enable, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
PGA input voltage noise density Low-power mode 7.5 nV/√Hz
High-resolution mode 5
Differential input impedance(1) CHOP enabled 1 GΩ
CHOP disabled 100
Common-mode input impedance 1 GΩ
IIB Input bias current 1 nA
Crosstalk f = 31.25 Hz –135 dB
Mux switch on-resistance Each switch 30 Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range AVSS + 0.4 AVDD – 0.4 V
PGA output impedance Differential 600 Ω
Output impedance tolerance ±10%
External bypass capacitance 10 100 nF
Modulator input impedance Low-power mode 110 kΩ
High-resolution mode 55
AC PERFORMANCE
SNR Signal-to-noise ratio(2) Low-power mode 117 121 dB
High-resolution mode 120 124
THD Total harmonic distortion(3) Low-power mode
PGA = 1, 2, 4, 8, 16 –122 -114 dB
PGA = 32 –117 -108
PGA = 64 –114
High-resolution mode
PGA = 1, 2, 4, 8, 16 -122 -114 dB
PGA = 32 -117 -110
PGA = 64 -114
SFDR Spurious-free dynamic range 123 dB
DC PERFORMANCE
Resolution 31 Bits
fDATA Data rate FIR filter mode 250 4000 SPS
Sinc filter mode 8000 128,000
Offset(11) Offset disabled ±50 ±200 µV
Offset and Chop disabled 300
75 mV offset 70 / PGA 75 / PGA 80 / PGA mV
100 mV offset 95 / PGA 100 / PGA 105 / PGA
Offset after calibration(4) 1 μV
Offset drift 0.03 μV/°C
CHOP disabled 0.5
Gain error(5) Low-power mode -1% -0.5% 0%
High-resolution mode –1.5% –1.0% –0.5%
Gain error after calibration(4) 0.0002%
Gain drift PGA = 1 2 ppm/°C
PGA = 16 9
Gain matching(9) 0.3% 0.8%
CMR Common-mode rejection fCM = 60 Hz, 1.25 VPP(6) 95 110 dB
PSR Power-supply rejection fPS = 60 Hz, 100 mVPP(6) AVDD, AVSS 80 90 dB
DVDD 90 115
VOLTAGE REFERENCE INPUTS
Reference input impedance Low-power mode 170 kΩ
High -resolution mode 85
DIGITAL FILTER RESPONSE
Pass-band ripple ±0.003 dB
Pass band (–0.01dB) 0.375 × fDATA Hz
Bandwidth (–3dB) 0.413 × fDATA Hz
High-pass filter corner 0.1 10 Hz
Stop band attenuation(7) 135 dB
Stop band 0.500 × fDATA Hz
Group delay Minimum phase filter(10) 5 / fDATA s
Linear phase filter 31 / fDATA
Settling time (latency) Minimum phase filter 62 / fDATA s
Linear phase filter 62 / fDATA
DIGITAL INPUTS/OUTPUTS
VOH High-level output voltage IOH = 1 mA 0.8 × DVDD V
VOL Low-level output voltage IOL = 1 mA 0.2 × DVDD V
Ilkg Input leakage 0 < VDIGITAL IN < DVDD ±10 μA
POWER SUPPLY
IAVDD
IAVSS 		Analog supply current Low-power mode
PGA = 1, 2, 4, 8 2 3.4 mA
PGA = 16, 32, 64 2.5 3.8
High-resolution mode
PGA = 1, 2, 4, 8 3.2 5.5 mA
PGA = 16, 32, 64 4 6
Standby mode 1 15 μA
Power-down mode 1 15
IDVDD Digital supply current Low-power mode 0.5 0.7 mA
High-resolution mode 0.6 0.8
Standby mode 25 50 μA
Power-down mode(8) 1 15
PD Power dissipation Low-power mode
PGA = 1, 2, 4, 8 12 20 mW
PGA = 16, 32, 64 14 22
High-resolution mode
PGA = 1, 2, 4, 8 18 30 mW
PGA = 16, 32, 64 22 33
Standby mode 90 250 μW
Power-down mode 10 125
(1) PGA chop mode is controlled by register setting.
(2) Inputs shorted; see Table 1 through Table 4 for more details.
(3) Input signal = 31.25 Hz, –0.5 dBFS.
(4) Calibration accuracy is on the level of noise reduced by four (calibration averages 16 readings).
(5) The PGA output impedance and the modulator input impedance results in systematic gain error.
(6) fCM is the input common-mode frequency. fPS is the power-supply frequency.
(7) Input frequencies in the range of N · fCLK / 1024 ± fDATA / 2 (where N = 1, 2, 3...) can intermodulate with the modulator chopper clock (and N multiples). At these frequencies, intermodulation = –120 dB, typ.
(8) CLK input stopped.
(9) Gain match relative to gain = 1.
(10) At dc; see Figure 50.
(11) Offset specification is input referred. The offset scales by the reference voltage (VREF).
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