8.3.3.1.4 Offset

The modulator can produce low-level idle tones that appear in the conversion data when there is no signal input or when low-level signal inputs are present to the ADC. The ADC provides an optional dc offset voltage designed to shift the idle tones to the stop band of digital filter response, where the idle tones are reduced. The internal offset is applied at the modulator input; therefore, the offset voltage is independent of PGA gain. Two offset voltage options are provided, 75 mV and 100 mV. The 75-mV offset is more effective to reduce idle tones under various gain, data rate, and chop mode settings.

The offset is enabled by the OFFSET1 and OFFSET0 bits (default is off). The offset voltage reduces the total available input range 4% (3% for the 75 mV value) before the onset of clipped conversion results. To restore the full range of the ADC, calibrate the offset voltage by the digital offset calibration register (OFC[2:0]). See Offset and Full-Scale Calibration Registers and Calibration Commands (OFSCAL and GANCAL) sections for details.