8.4.3 Master Clock Input (CLK)

The ADS1284 requires a clock for operation. The specified clock frequency is 4.096 MHz and is applied to the CLK pin. The ADC data rates scale with clock frequency, however there is no benefit in noise reduction by reducing clock frequency; select a slower data to reduce noise.

As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the clock source.