The ADC integrates calibration registers to correct offset and gain errors. As shown in Equation 6 and Figure 8-20, the 24-bit offset value (OFFSET[23:0]) is subtracted from the filter data before multiplication by the 24-bit gain value (GAIN[23:0]), divided by 400000h. The data are clipped to 32 bits to yield the final output. The offset operation is bypassed when the high-pass filter is enabled.