ZHCSQZ8A May 2022 – December 2022 ADS1285
PRODUCTION DATA
The PGA is a low-noise, chopper-stabilized differential amplifier that extends the ADC dynamic range performance. The PGA provides analog gains from 1 to 16, with gains of 32 and 64 provided by digital scaling. The PGA output signal is routed to the CAPP and CAPN pins through 270-Ω resistors. Connect an external 10-nF, C0G-dielectric capacitor across these pins. An antialias filter is formed by these components to attenuate the signal level at the modulator aliasing frequency (fMOD).
As shown in Figure 8-4, the buffer is used between the PGA and the modulator. Connect two 47-nF, C0G-dielectric capacitors from each buffer output to AVSS (CAPBP and CAPBN). A voltage charge pump increases the buffer input voltage headroom. Connect an external 4.7-nF capacitor between CAPC and AGND for charge pump operation.
The PGA gain is programmed by the GAIN[2:0] bits of the CONFIG1 register. Table 8-2 shows the PGA gain settings and buffer selection. The PGA gains and input signal range are irrespective of the voltage reference.
| GAIN[2:0] REGISTER BITS | PGA GAIN | INPUT SIGNAL RANGE (VPP) |
|---|---|---|
| 000 | 1 | ±2.5 |
| 001 | 2 | ±1.25 |
| 010 | 4 | ±0.625 |
| 011 | 8 | ±0.3125 |
| 100 | 16 | ±0.15625 |
| 101 | 32 | ±0.078125 |
| 110 | 64 | ±0.0390625 |
| 111 | Buffer mode, gain = 1 | ±2.5 |
Observe the PGA input and output voltage headroom specification. Figure 8-5 shows the input and output voltage headroom when operating with AVDD1 = 5 V, an input common-mode voltage (VCM) = 2.5 V, a differential input voltage = ±2.5 VPP, and at gain = 1. The absolute minimum and maximum PGA input voltage (1.25 V and 3.75 V) is ±1/2 of the differential signal voltage plus the common-mode voltage. The PGA provides 0.15-V input voltage margin at the negative peak and 0.4-V input voltage margin at the positive peak. As shown in the figure, the PGA gain increases by × 1.5 when the ADC is operated with 4.096-V or 5-V voltage references. The PGA provides 0.475-V output voltage margin at the positive and negative peaks.
When operating with AVDD1 = 3.3 V, the PGA cannot support ±2.5-VPP input signals. Use the buffer for ±2.5-VPP input signals. For ±1.25-VPP input signals (PGA gain = 2), the input headroom is increased by increasing the common-mode voltage by 0.1 V to AVSS + 1.75 V. Figure 8-6 illustrates the input and output operating headroom for AVDD1 = 3.3 V, VCM = 1.75 V, input signal = ±1.25 VPP, and gain = 2. The PGA uses normal gain scaling when VREF = 2.5 V.