The sample rate converter (SRC) compensates clock frequency error by resampling the modulator data at a new rate set by the compensation factor written to the SRC registers. The frequency compensation range is ±244 ppm with 7.45-ppb (1 / 2²⁷) resolution.

Clock frequency error is compensated by writing a value to the SCR0 and SRC1 registers. The register value is in 2's-complement format for positive and negative frequency error compensation. Positive register data values decrease the data rate frequency (increases the period). The new data rate frequency is observed by the frequency of the DRDY signal.

Table 8-7 shows example values of frequency compensation. 8000h disables the sample rate converter. 0000h passes the data through with no compensation but adds an 8 / f_CLK delay to the time delay of SYNC input to the DRDY pulses.

Resynchronize the ADC after the sample rate converter is enabled or disabled.

Because the SRC is a digital function, operation is deterministic without error. The SRC trim value can be written all at the same time, or written incrementally up to a target value to minimize the step change of frequency. Use the multibyte command operation to write to the SRC registers and complete the write operation 256 CLK cycles before the DRDY falling edge. This procedure loads the high and low bytes simultaneously before they are internally processed. See Figure 6-7 for details.