The digital filter decimates and filters the modulator data to provide the high-resolution output data. By adjusting the amount of filtering though the OSR, trade-offs can be made between total noise and bandwidth. Increasing the OSR lowers total noise while decreasing the signal bandwidth.

As shown in Figure 8-10, the sample rate converter (SRC) receives data from the modulator prior to input to the digital filter block. See the Section 8.4.5 section for details.

The digital filter is comprised of three sections: a variable-decimation sinc filter; a variable-coefficient, fixed-decimation FIR filter; and a programmable high-pass filter (IIR). The desired filter path is selected by the FILTER[1:0] bits of the CONFIG0 register. The sinc filter provides partially filtered data, bypassing the FIR and HPF filters and user calibration. For fully filtered data, select the FIR filter option. The IIR filter stage removes dc and low-frequency data The FIR and the combined FIR + IIR filter are routed to the user calibration block and output code clipping block. See the Section 8.4.6 section for details of user calibration.