ZHCSQZ8A May   2022  – December 2022 ADS1285

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
    7. 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 PGA and Buffer
        1. 8.3.2.1 Programmable Gain Amplifier (PGA)
        2. 8.3.2.2 Buffer Operation (PGA Bypass)
      3. 8.3.3 Voltage Reference Input
      4. 8.3.4 IOVDD Power Supply
      5. 8.3.5 Modulator
        1. 8.3.5.1 Modulator Overdrive
      6. 8.3.6 Digital Filter
        1. 8.3.6.1 Sinc Filter Section
        2. 8.3.6.2 FIR Filter Section
        3. 8.3.6.3 Group Delay and Step Response
          1. 8.3.6.3.1 Linear Phase Response
          2. 8.3.6.3.2 Minimum Phase Response
        4. 8.3.6.4 HPF Stage
      7. 8.3.7 Clock Input
      8. 8.3.8 GPIO
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Reset
      4. 8.4.4 Synchronization
        1. 8.4.4.1 Pulse-Sync Mode
        2. 8.4.4.2 Continuous-Sync Mode
      5. 8.4.5 Sample Rate Converter
      6. 8.4.6 Offset and Gain Calibration
        1. 8.4.6.1 OFFSET Register
        2. 8.4.6.2 GAIN Register
        3. 8.4.6.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Data Ready (DRDY)
      2. 8.5.2 Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  Single Byte Command
        2. 8.5.3.2  WAKEUP: Wake Command
        3. 8.5.3.3  STANDBY: Software Power-Down Command
        4. 8.5.3.4  SYNC: Synchronize Command
        5. 8.5.3.5  RESET: Reset Command
        6. 8.5.3.6  Read Data Direct
        7. 8.5.3.7  RDATA: Read Conversion Data Command
        8. 8.5.3.8  RREG: Read Register Command
        9. 8.5.3.9  WREG: Write Register Command
        10. 8.5.3.10 OFSCAL: Offset Calibration Command
        11. 8.5.3.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2.3 Application Curves

Table 9-1 lists the effect of source resistance (RS) and device input current noise on dynamic range performance. Selected values of RS and input current noise, obtained from the input current noise distribution of Figure 9-2 (1.5 pA/√Hz and 3 pA/√Hz), are evaluated. Thermal noise voltage of the source resistance, input current noise × source resistance, and ADC input-referred noise voltage are summed as RMS values to derive the total noise. Dynamic range is calculated from the total noise result.

Figure 9-2 PGA Input Current Noise Distribution
Table 9-1 Source Resistance Noise
RS (Ω) GAIN in NOISE (pA/√Hz) RS NOISE (μV) in × RS NOISE (μV) ADC SELF-NOISE  (μV) TOTAL NOISE (μV) DR (dB)
0 1 1.5 0 0 0.44 0.44 132.1
3 0 0.44 132.1
16 1.5 0 0.11 0.11 120.1
3 0 0.11 120.1
1000 1 1.5 0.06 0.024 0.44 0.445 132.0
3 0.048 0.446 132.0
16 1.5 0.024 0.11 0.127 118.8
3 0.048 0.134 118.4
5000 1 1.5 0.13 0.11 0.44 0.472 131.5
3 0.22 0.508 130.8
16 1.5 0.11 0.11 0.202 114.8
3 0.21 0.277 112.0

Data for the analysis is shown for low-power mode operation over a 206-Hz noise bandwidth (fDATA = 500 SPS). For PGA gain = 1, 5000-Ω source resistance has a minor effect on dynamic range performance. However, at PGA gain = 16, dynamic range performance can degrade from –5 dB to –8 dB depending on the level of device input current noise. 1000-Ω source resistance has 1.6-dB degradation at gain = 16 for input current noise density = 3 pA/√Hz.

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