ZHCSQZ8A May 2022 – December 2022 ADS1285
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
- 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
- 6.8 Timing Diagrams
- 6.9 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Programming
- 8.5.1 Serial Interface
- 8.5.2 Conversion Data Format
- 8.5.3
Commands
- 8.5.3.1 Single Byte Command
- 8.5.3.2 WAKEUP: Wake Command
- 8.5.3.3 STANDBY: Software Power-Down Command
- 8.5.3.4 SYNC: Synchronize Command
- 8.5.3.5 RESET: Reset Command
- 8.5.3.6 Read Data Direct
- 8.5.3.7 RDATA: Read Conversion Data Command
- 8.5.3.8 RREG: Read Register Command
- 8.5.3.9 WREG: Write Register Command
- 8.5.3.10 OFSCAL: Offset Calibration Command
- 8.5.3.11 GANCAL: Gain Calibration Command
- 8.6
Register Map
- 8.6.1
Register Descriptions
- 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
- 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
- 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
- 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
- 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
- 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
- 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
- 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
- 8.6.1
Register Descriptions
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.3.6.3.2 Minimum Phase Response
The minimum phase filter provides a short group delay for data from filter input to filter output. Figure 8-18 shows the group delay for minimum and linear phase filters. The group delay of the minimum phase filter is a function of signal frequency. The PHASE bit of the CONFIG0 register programs the filter phase.
Figure 8-18 FIR Group Delay (fDATA = 500 SPS)