8.4.3 Offset

As with most ΔΣ modulators, the ADC can produce low-level idle tones (typically 140 dB below the full-scale amplitude). The idle tones appear as low-frequency components in the output data when either no- or low-level signals are present. Typically, idle tones do not occur when high-level signals are present. The ADC incorporates an internal offset option that is intended to reduce the amplitudes of the tone. The offset is recommended for the low-power mode operation only and is not recommended for the high-resolution mode operation. Use the external offset circuit illustrated in the Application Information section for idle tone reduction in high-resolution mode operation.

The offset is enabled by the OFFSET bit of the ID_CFG register. The offset voltage is 50 mV. The 50-mV offset leads to 2% reduction of the input range that is restored by calibrating the offset voltage by use of the offset calibration registers. Offset correction is accomplished by performing offset calibration, or to provide nominal correction, write 029700h to the calibration registers.