8.4.7.1 Read-Data-Continuous Mode (RDATAC)

In read-data-continuous mode, conversion data are read without the need of a read data command. When DRDY asserts low (indicating new data), the MSB of data appears on DOUT. Read data by applying the serial interface clock on SCLK; see Figure 3 for DRDY to DOUT timing.

As shown in Figure 59, conversion data are read by first driving CS low and then shifting the data by applying the serial interface clock to SCLK. Latch the data on the rising edge of SCLK. On the first falling edge of SCLK, the ADC returns DRDY high. After all 32 bits of conversion data are read, further SCLK transitions result in DOUT driven low. If desired, the read operation can be stopped after 24 bits. A new read cycle is started when new conversion data are available. The data read operation must be completed four CLK periods prior to the next DRDY falling edge, otherwise the data are overwritten with new conversion data.

1. DOUT is in tri-state mode when CS is high. SCLK arrows indicate when the data are latched.

Figure 59. Read-Data-Continuous Mode