8.5.1.5 Serial Interface Timeout

When CS is low, the serial interface times-out (resets) if SCLK is held low for 64 DRDY cycles. Reset of the serial interface terminates commands in progress. When reset, the next SCLK pulse starts a new communication cycle. To prevent timeout and reset of the serial interface, provide at least one SCLK pulse for every 64 DRDY pulses.