ZHCSK67B June 2017 – August 2019 ADS1287
PRODUCTION DATA.
The commands listed in Table 19 control ADC operation. Most commands are stand-alone (that is, one byte in length); the register read and write command lengths are two bytes, plus additional data bytes that represent the actual register data.
COMMAND | TYPE | DESCRIPTION | 1ST COMMAND BYTE(1)(2) | 2ND COMMAND BYTE(3) |
---|---|---|---|---|
WAKEUP | Control | Wake-up from standby mode | 0000 000X (00h or 01h) | |
STANDBY | Control | Enter standby mode | 0000 001X (02h or 03h) | |
SYNC | Control | Synchronize ADC conversions | 0000 010X (04h or 5h) | |
RESET | Control | Reset the ADC | 0000 011X (06h or 07h) | |
RDATAC | Control | Read data continuous mode | 0001 0000 (10h) | |
SDATAC | Control | Stop read data continuous mode | 0001 0001 (11h) | |
RDATA | Data | Read data by command(4) | 0001 0010 (12h) | |
RREG | Register | Read nnnnn registers at address rrrrr(4) | 001r rrrr (20h + 000r rrrr) | 000n nnnn (00h + n nnnn) |
WREG | Register | Write nnnnn registers at address rrrrr | 010r rrrr (40h + 000r rrrr) | 000n nnnn (00h + n nnnn) |
OFSCAL | Calibration | Offset calibration | 0110 0000 (60h) | |
GANCAL | Calibration | Gain calibration | 0110 0001 (61h) |
CS must remain low for the duration of the command-byte sequence. Provide a 24 / fCLK delay between commands, between bytes within a command, and from the last byte of a command prior to returning CS high. The required delay starts from the last SCLK rising edge of the preceding byte to the first SCLK rising edge of the following byte; see Figure 2. The delay between data bytes is not necessary when reading conversion data.