The sample rate converter (SRC) compensates clock frequency error by resampling the modulator data at a new rate set by a compensation factor written to the SRC registers. The compensation range is ±244ppm with 7.45ppb (1 / 2²⁷) resolution.

Clock frequency error is compensated by writing a value to the SCR0 and SRC1 registers. The register value is in two's-complement format for positive and negative error compensation. Positive register data values decrease the data rate frequency (increases the period). The compensated data rate frequency is observed by the frequency of the DRDY signal.

Table 7-7 shows example values of SRC compensation. 8000h disables the sample rate converter. 0000h passes the data through with no compensation but adds an 8 / f_CLK delay to the existing time delay of SYNC input to the DRDY pulses.

Resynchronize the ADC after the sample rate converter is enabled or disabled.

Because the SRC is a digital function, operation is deterministic without error. When the target compensation value is determined, the value can be immediately written to the ADC, or incrementally written up to the determined value to reduce the effect of step changes in the output frequency. Because two bytes are used for the SRC registers, use the multibyte command operation to write to the SRC registers and complete the write operation 256 CLK cycles before the DRDY falling edge. This procedure simultaneously loads the high and low bytes for compensation. See Figure 5-7 for details.