The ADC is synchronized by the SYNC pin or by the SYNC command, resulting in restart of the digital filter cycle. Synchronization by the pin occurs on the next rising edge of CLK after SYNC is taken high on the falling edge of CLK. Synchronization by the SYNC command occurs on the rising edge of CLK following the eighth bit of the command.

The following results in loss of synchronization:

• When a power-up cycle or ADC reset occurs
• When the hardware or software power-down modes are entered
• The following register mode changes occur:
  • DR[2:0] (data rate)
  • PHASE (filter phase)
  • SYNC (synchronization mode)
  • SRC[1:0] (sample rate converter enabled or disabled)

There are two synchronization control modes: pulse sync and continuous sync. The synchronization mode is programmed by the SYNC bit of the ID/SYNC register.