Conversion data are read and ADC configuration is made through the SPI-compatible serial interface. The interface consists of four signals: CS, SCLK, DIN, and DOUT. DRDY asserts low when conversion data are ready. The serial interface is passive (peripheral mode), where the serial clock (SCLK) is an input. The ADC operates in SPI mode 0, where CPOL = 0 and CPHA = 0. In mode 0, SCLK idles low and data are updated on the SCLK falling edges and are read on the SCLK rising edges.