Power-down is engaged by taking the PWDN pin low, or by software control, by sending the STANDBY command. To exit power-down, take PWDN high or send the WAKEUP command to exit software power-down (with the clock running). Power-down disables the analog circuit; however, the digital LDO (CAPD pin) remains biased, drawing a small bias current from IOVDD. In comparison, software power-down draws larger IOVDD bias current. In both power-down modes, the ac signals of the digital outputs are stopped but remain driven high or low. The digital inputs must not be allowed to float; otherwise, leakage current can flow from the IOVDD supply. Reset the ADC if the clock is interrupted in power-down. Synchronization is lost in power-down; therefore, resynchronize the ADC.