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ZHCSA21C FEBRUARY 2013 – December 2014 ADS1293

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RSG|28
- MPQF190A

散热焊盘机械数据 (封装 | 引脚)

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7 Specifications

7.1 Absolute Maximum Ratings

See ⁽¹⁾⁽²⁾.

		MIN	MAX	UNIT
Analog Supply Voltage, VDD		–0.3	6.0	V
Digital Supply Voltage, VDDIO		–0.3	6.0	V
Voltage on any Input Pin		–0.3 to (VDD + 0.3)		V
Input Current at Any Pin			±10	mA
Max Junction Temperature⁽³⁾			150	°C
T_stg	Storage temperature	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to the ground pin, unless otherwise specified.

(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by T_J(MAX), θ_JA, and the ambient temperature, T_A. The maximum allowable power dissipation P_DMAX = (T_J(MAX) – T_A)/ θ_JA or the number given in , whichever is lower.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Analog Supply Voltage, VDD		2.7	5.5	V
Digital I/O Supply Voltage	VDD > 3.6 V	1.65	3.6	V
Digital I/O Supply Voltage	VDD ≤ 3.6 V	1.65	VDD	V
Supply Ground		VSS = VSSIO
Full Scale Differential Input Voltage Range, DIVR			±400	mV
Temperature Range⁽²⁾		–20	85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS1293	UNIT
		LLP
		28 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	29	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by T_J(MAX), R_θJA, and the ambient temperature, T_A. The maximum allowable power dissipation P_DMAX = (T_J(MAX) – T_A)/R_θJA or the number given in , whichever is lower.

7.5 Electrical Characteristics⁽¹⁾

Unless otherwise noted, all limits are specified at T_A = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, 1.65 V ≤ VDDIO ≤ MIN(3.6 V, VDD), VREF = 2.4 V, f_OSC = 409.6 kHz, 1-µF low-ESR capacitor between CVREF and GND, 0.1-µF capacitor between RLDREF and GND.

PARAMETER		TEST CONDITIONS	MIN⁽³⁾	TYP⁽²⁾	MAX⁽³⁾	UNIT
POWER SUPPLY (VDD, VDDIO)
VDD	Analog Supply Voltage	T_MIN ≤ T_A ≤ T_MAX	2.7		5.5	V
IVDD	Analog Supply Current	Power-down mode		80		µA
		T_MIN ≤ T_A ≤ T_MAX			125	µA
		Standby mode		120		µA
		T_MIN ≤ T_A ≤ T_MAX			175	µA
		1 chan, WILSON OFF, RLD OFF, CMDET OFF, LOD OFF, low-power		205		µA
		T_MIN ≤ T_A ≤ T_MAX			290
		1 chan, WILSON OFF, RLD OFF, CMDET OFF, LOD OFF, high-res		335
		T_MIN ≤ T_A ≤ T_MAX			490
		3 chan, WILSON OFF, RLD OFF, CMDET OFF, LOD OFF, low-power		350
		T_MIN ≤ T_A ≤ T_MAX			520
		3 chan, WILSON ON, RLD ON, CMDET ON, LOD ON, low-power, low cap-drive		440
		T_MIN ≤ T_A ≤ T_MAX			595
		3 chan, WILSON ON, RLD ON, CMDET ON, LOD ON, high-res, low cap-drive		835
		T_MIN ≤ T_A ≤ T_MAX			1120
		3 chan, WILSON ON, RLD ON, CMDET ON, LOD ON, high-res, high cap-drive		960
		T_MIN ≤ T_A ≤ T_MAX			1300
VDDIO	IO Supply Voltage	VDD > 3.6 V T_MIN ≤ T_A ≤ T_MAX	1.65		3.6	V
VDDIO	IO Supply Voltage	VDD ≤ 3.6 V T_MIN ≤ T_A ≤ T_MAX	1.65		VDD	V
IVDDIO	Quiescent Current IO Supply			0.6		µA
ANALOG INPUTS (IN1-IN6)
I_B	Input Bias Current	T_A= 25°C, LOD OFF	–175		175	pA
I_B	Input Bias Current	T_A = 85°C, LOD OFF T_MIN ≤ T_A ≤ T_MAX	–13		13	nA
RIN	Differential Input Resistance			500		MΩ
EMIRR	Electromagnetic Interference Rejection Ratio, IN+, IN-, and VDD	f = 400 MHz		92		dB
		f = 900 MHz		107		dB
		f = 1.8 GHz		98		dB
		f = 2.4 GHz		86		dB
ANALOG FRONT END
DIVR	Differential Input Voltage Range	T_MIN ≤ T_A ≤ T_MAX	–400		400	mV
CMVR	Common-Mode Voltage Range for full DIVR	T_MIN ≤ T_A ≤ T_MAX	0.95		VDD – 0.95	V
V_OS	Input-Referred Offset Voltage			±16		µV
V_OS	Input-Referred Offset Voltage	T_MIN ≤ T_A ≤ T_MAX	–87		87	µV
CMRR	Common-Mode Rejection Ratio	50 / 60 Hz, VCM_DC = RLDREF, VCM_AC = 1.2V_PP		100		dB
V_e-ECG	Input-Referred Voltage Noise for ECG⁽⁵⁾	0.1 - 215 Hz, low-power mode		23		µV_PP
		T_MIN ≤ T_A ≤ T_MAX			30.5
		0.1 - 215 Hz, high-resolution mode		15
		T_MIN ≤ T_A ≤ T_MAX			23.95
		0.1 - 40 Hz, low-power mode		10
		T_MIN ≤ T_A ≤ T_MAX			23.1
		0.1 - 40 Hz, high-resolution mode		7
		T_MIN ≤ T_A ≤ T_MAX			10.3
V_e-PACE	Input-Referred Voltage Noise for Pace	1 - 1280 Hz, high-resolution mode, double pace data rate		0.4		mV_PP
N_e	Input-Referred Noise Density	0.1 - 215 Hz, low-power mode		240		nV/√Hz
		T_MIN ≤ T_A ≤ T_MAX			315
		0.1 - 215 Hz, high-resolution mode		155
		T_MIN ≤ T_A ≤ T_MAX			250
PSRR	Power Supply Rejection Ratio	50 / 60 Hz		94		dB
XTLK	Crosstalk between channels	Crosstalk from driven channel to zero input channel		–105		dB
ENOB-ECG	Effective Number of Bits for ECG	215-Hz bandwidth, low-power mode		17.8		bits
		T_MIN ≤ T_A ≤ T_MAX	17.4			bits
		215 Hz bandwidth, high-resolution mode		18.4		bits
		T_MIN ≤ T_A ≤ T_MAX	17.8			bits
ENOB-PACE	Effective Number of Bits for Pace	1280-Hz bandwidth, high-resolution mode, double pace data rate		13.7		bits
RS-ECG	Sample Rate ECG Channel	See Table 8, Table 9, Table 10 and Table 11 T_MIN ≤ T_A ≤ T_MAX	25		6400	sps
RS-PACE	Sample Rate PACE Channel	T_MIN ≤ T_A ≤ T_MAX	3.2		25.6	ksps
TSKEW	Sample Time Skew Between Channels	Multichip simultaneous sampling architecture		0		µs
INTERNAL REFERENCE (REF)
V_REF	Internal Reference Voltage			2.4		V
	Internal Reference Accuracy			±0.5%
	Internal Reference Drift			±11		ppm/°C
	Internal Reference Start-up Time			5		ms
BATTERY MONITOR
Division	(VDD-V_REF)/factor			3.246		V/V
	Division Accuracy			±0.25%
TEST REFERENCE
	(V_REF-VSS)/factor			12		V/V
	Division Accuracy			±0.1%
	Current Consumption			3.5		μA
RIGHT-LEG DRIVE AMPLIFIER (RLD Amp)
V_OS	Input-Referred Offset Voltage			±5		mV
CMVR	Common-Mode Voltage Range	T_MIN ≤ T_A ≤ T_MAX	0.5		VDD – 0.5	V
GBW	Programmable Gain Bandwidth	Low-bandwidth mode		50		kHz
GBW	Programmable Gain Bandwidth	High-bandwidth mode		200		kHz
SR	Slew Rate	Low-bandwidth mode		25		mV/μs
SR	Slew Rate	High-bandwidth mode		90		mV/μs
Cl_MAX	Programmable Capacitive Load Driving Capability	High-bandwidth, Low cap-drive mode (see Table 5)		400		pF
Cl_MAX	Programmable Capacitive Load Driving Capability	Low-bandwidth, High cap-drive mode (see Table 5)		8		nF
IVDD	Quiescent Power Consumption	Low-bandwidth, Low cap-drive mode		20		μA
		T_MIN ≤ T_A ≤ T_MAX			36	μA
		High-bandwidth, High cap-drive mode		60		μA
		T_MIN ≤ T_A ≤ T_MAX			91	μA
RIGHT-LEG DRIVE REFERENCE
RLD_REF	Output Voltage	Unloaded		(VDD – VSS)/2.2		V
COMMON-MODE DETECTOR AMPLIFIER (CMDET Amp)
CMVR	Common-Mode Voltage Range	T_MIN ≤ T_A ≤ T_MAX	0.5		VDD – 0.5	V
BW	Programmable Bandwidth	Low-bandwidth mode		50		kHz
BW	Programmable Bandwidth	High-bandwidth mode		150		kHz
SR	Slew Rate	Low-bandwidth mode		25		mV/μs
SR	Slew Rate	High-bandwidth mode		90		mV/μs
Cl_MAX	Programmable Capacitive Load Driving Capability	High-bandwidth mode, Low capdrive mode (see Table 4)		400		pF
Cl_MAX	Programmable Capacitive Load Driving Capability	Low-bandwidth mode, High cap- drive mode (see Table 4)		8		nF
IVDD	Power Consumption (Selected Leads)	N leads, low-bandwidth mode, low cap-drive mode		21 + 3 × N		μA
IVDD	Power Consumption (Selected Leads)	N leads, high-bandwidth mode, high cap-drive mode		61 + 3 × N		μA
WILSON REFERENCE CIRCUIT
IVR	Input Voltage Range	T_MIN ≤ T_A ≤ T_MAX	0.5		VDD – 0.5	V
BW	Bandwidth	3 buffers ON		50		kHz
SR	Slew Rate	3 buffers ON		45		mV/μs
N_e	Noise Density	At 10 Hz		60		nV/√Hz
V_e	Input-Referred Noise for Wilson Reference Amp	0.1 - 200 Hz, 3 buffers ON		5.5		μV_PP
IVDD	Power Consumption (Selected Leads)	N leads, low-power mode		7 × N		μA
LEAD-OFF DETECTION
IEXC	Excitation Current	Programmable: Min. code 0x01 (See Lead-Off Detection (LOD))		8		nA
IEXC	Excitation Current	Programmable: Max. code 0xFF (See Lead-Off Detection (LOD))		2040		nA
IEXC_TOL	Excitation Current Accuracy			25%
FEXC	Excitation Frequency	AC LOD mode, programmable, minimum (see Analog AC Lead-Off Detect )		6.1		Hz
FEXC	Excitation Frequency	AC LOD mode, programmable, maximum (see Analog AC Lead-Off Detect)		12.5		kHz
VTH_DC	DC Lead-Off Comparator Threshold			VDD – 0.5		V
V_HYST	Comparator Hysteresis	DC lead-off mode		55		mV
IVDD	Current Consumption	Programmed excl. excitation current		25		μA
ANALOG PACE CHANNEL
	Gain			3.5		V/V
BW	–3dB Bandwidth			50		kHz
	Output Reference			RLDREF		V
V_OS	Input-Referred Offset Voltage			±1.3		mV
DIVR	Differential Input Voltage Range	2.7 V ≤ VDD < 3.3 V T_MIN ≤ T_A ≤ T_MAX	–330		330	mV
DIVR	Differential Input Voltage Range	3.3 V ≤ VDD T_MIN ≤ T_A ≤ T_MAX	–400		400	mV
CMVR	Common-Mode Voltage Range for full DIVR	T_MIN ≤ T_A ≤ T_MAX	0.95		VDD – 1.1	V
CMRR	Common-Mode Rejection Ratio	0.5 V ≤ VCM ≤ VDD-1.5 V		85		dB
PSRR	Power Supply Rejection Ratio	3 V ≤ VDD ≤ 5 V, VCM=RLDREF		80		dB
SR	Slew Rate			35		mV/µs
	Overload Recovery			100		µs
V_e-APACE	Input-Referred Noise for Analog Pace	VCM = RLDREF, 0.1 kHz - 20 kHz		105		µV_PP
IVDD	Current Consumption			29		µA
CLOCK
f_OSC	Internal Clock Frequency	f_CRYSTAL = 4.096 MHz		409.6		kHz
	Internal Clock Duty Cycle			50%
TSTART	Internal Clock Start-up Time	f_CRYSTAL= 4.096 MHz		15		ms
IVDD	Internal Clock Power Consumption			83		µA
f_EXT	External Clock Frequency⁽⁴⁾	T_MIN ≤ T_A ≤ T_MAX	370	409.6	450	kHz
	External Clock Duty Cycle⁽⁴⁾	T_MIN ≤ T_A ≤ T_MAX	40%	50%	60%
DIGITAL INPUT / OUTPUT CHARACTERISTICS
V_IH	Logical “1” Input Voltage	T_MIN ≤ T_A ≤ T_MAX	0.8 × VDDIO			V
V_IL	Logical “0” Input Voltage	T_MIN ≤ T_A ≤ T_MAX			0.2 × VDDIO	V
V_OH	Logical “1” Output Voltage	I_SOURCE = 400 µA, Digital output high-drive mode T_MIN ≤ T_A ≤ T_MAX	VDDIO – 0.075			V
V_OH	Logical “1” Output Voltage	I_SOURCE = 400 µA, Digital output low-drive mode T_MIN ≤ T_A ≤ T_MAX	VDDIO – 0.15			V
V_OL	Logical “0” Output Voltage	I_SINK = 400 µA, Digital output high-drive mode T_MIN ≤ T_A ≤ T_MAX			VSSIO + 0.075	V
V_OL	Logical “0” Output Voltage	I_SINK = 400 µA, Digital output low-drive mode T_MIN ≤ T_A ≤ T_MAX			VSSIO + 0.15	V
I_IOHL	Digital IO Leakage Current	SYNCB and RESETB pins, with 1-MΩ internal pullup resistor		±1		µA
I_IOHL	Digital IO Leakage Current	Other digital I/O pins T_MIN ≤ T_A ≤ T_MAX	–500		500	nA

(1) Typical specifications are estimations only and are not ensured.

(2) Typical values represent the most likely parameter norms at T_A = 25°C and at the at the time of product characterization and are not ensured.

(3) Datasheet min/max specification limits are specified by test, unless otherwise noted.

(4) Specified by design; not production tested.

(5) At least 1000 consecutive readings are used to calculate the peak-to-peak noise in production.

7.6 Write Timing Requirements

Unless otherwise noted, all limits specified at T_A = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, 1.65 ≤ VDDIO ≤ MIN (3.6 V, VDD), VREF = 2.4 V, f_OSC = 409.6-kHz and a 10-pF capacitive load in parallel with a 10-kΩ load on SDO.

			MIN	MAX	UNIT
F_SCLK	Serial Clock Frequency			20	MHz
t_PH	SCLK Pulse Width - High	F_SCLK = 20 MHz	0.4/F_SCLK		s
t_PL	SCLK Pulse Width - Low	F_SCLK = 20 MHz	0.4/F_SCLK		s
t_SU	SDI Set-up Time		5		ns
t_H	SDI Hold Time		5		ns

Figure 1. Write Timing Diagram

7.7 Read Timing Requirements

Unless otherwise noted, all limits specified at T_A = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, 1.65 ≤ VDDIO ≤ MIN(3.6 V, VDD), VREF = 2.4 V, f_OSC = 409.6-kHz and a 10-pF capacitive load in parallel with a 10-kΩ load on SDO.

			MIN	NOM	MAX	UNIT
t_ODZ	SDO Driven-to-Tristate Time	Measured at 10% / 90% point			15	ns
t_OZD	SDO Tristate-to-Driven Time	Measured at 10% / 90% point			15	ns
t_OD	SDO Output Delay Time				10	ns
t_CSS	CSB Set-up Time		5			ns
t_CSH	CSB Hold Time		5			ns
t_IAG	Inter-Access Gap		10			ns
t_DRDYB	Data Ready Bar at every 1/ODR second, see Figure 25			4/f_OSC		s

Figure 2. Read Timing Diagram

7.8 Typical Characteristics

All plots at T_A = 25°C, VDD = 3.3 V, VDDIO = 1.8 V, VSS = VSSIO = 0 V, internal VREF = 2.4 V, VCM = RLDREF, internal f_OSC = 409.6 kHz, data rate = 1067 sps, and High-Resolution mode, unless otherwise noted.