By default, the ADS130B02-Q1 is configured to operate with an external clock, such as at power-up. An LVCMOS clock must be provided at the CLKIN pin continuously when the ADS130B02-Q1 is running in normal operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a trade-off between power consumption and noise performance.

The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: high-resolution (HR), low-power (LP), or very-low-power (VLP). Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. Follow the guidance for the external clock frequency provided in the Section 6.3 table corresponding to the intended power mode in order for the device to perform according to the specification.