Each channel of the ADS130B02-Q1 features an integrated programmable gain amplifier (PGA) that provides gains of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINn bits for each channel in the GAIN register.

Varying the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 2 describes the relationship between FSR and gain. Equation 2 uses the internal reference voltage, 1.2 V, as the scaling factor without accounting for gain error caused by tolerance in the reference voltage.

Table 8-1 shows the corresponding full-scale ranges for each gain setting.

The input impedance of the ADS130B02-Q1 depends on three factors: the main clock frequency (f_MCLK), the selected OSR setting, and the global-chop mode setting. Table 8-2 shows typical input impedance values for
f_MCLK = 8.192 MHz. The input impedance scales indirectly proportional with the MCLK frequency, which means that at f_MCLK = 4.096 MHz, the impedance values in Table 8-2 increase by a factor of 2. Minimize the output impedance of the circuit that drives the ADS130B02-Q1 inputs to obtain the best possible gain error, INL, and distortion performance.