ZHCSEV8D March 2016 – January 2018 ADS131A02 , ADS131A04
PRODUCTION DATA.
For a multiple register read back, the command status response exceeds the 16-bit reserved device word space, causing an overflow to additional command status words. The first command status response is an acknowledgment of multiple registers to be read back and the additional command status responses shift out register data. The command status response details are shown below:
First command status response: 001a aaaa nnnn nnnn, where a aaaa is the starting register address and nnnn nnnn is the number of registers to read minus one (n-1).
Additional command status responses: dddd dddd eeee eeee , where dddd dddd is the register data from the first register read back and eeee eeee is the register data from the second read back register.
The number of additional command status responses across multiple frames is dependent on the number of registers to be read back. During a RREGS command status response, any new input commands are ignored until the command completes by shifting out all necessary command status responses. If the resulting address extends beyond the usable register space, zeroes are returned for any remaining non-existent registers. An example of the command response to reading four registers using a RREGS command is shown in Figure 76.