ZHCSN79 September   2021 ADS131B02-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Internal Test Signals
      6. 8.3.6  Clocking
        1. 8.3.6.1 External Clock Using CLKIN Pin
        2. 8.3.6.2 Internal Oscillator
      7. 8.3.7  ΔΣ Modulator
      8. 8.3.8  Digital Filter
        1. 8.3.8.1 Digital Filter Implementation
          1. 8.3.8.1.1 Fast-Settling Filter
          2. 8.3.8.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.8.2 Digital Filter Characteristic
      9. 8.3.9  Calibration Registers
      10. 8.3.10 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Synchronization
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  SPI Communication Frames
        7. 8.5.1.7  SPI Communication Words
        8. 8.5.1.8  Short SPI Frames
        9. 8.5.1.9  Communication Cyclic Redundancy Check (CRC)
        10. 8.5.1.10 SPI Timeout
      2. 8.5.2 ADC Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0110 0110)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Troubleshooting
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Minimum Interface Connections
      5. 9.1.5 Multiple Device Configuration
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Capacitor Requirement
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.1 Noise Measurements

Adjust the data rate and gain to optimize the ADS131B02-Q1 noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS131B02-Q1 noise performance using the 1.2-V internal reference and a 3.3-V analog power supply. The data are representative of typical noise performance at TA = 25°C when fMCLK = 8.192 MHz. The modulator clock frequency fMOD = fMCLK / 2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the RMS noise for each reading. Table 7-2 shows the effective resolution calculated from the noise data. Equation 1 calculates effective resolution. In each case, VREF corresponds to the internal 1.2-V reference. In global-chop mode, noise is improved by a factor of √2.

The noise performance scales with the oversampling rate (OSR) and gain settings, but is independent from the configured power mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the main clock frequency for the different power modes.

Equation 1. GUID-616B3C3D-E080-4631-8BBF-7989C9FBF52E-low.gif
Table 7-1 Noise (μVRMS) at TA = 25°C
OSR DATA RATE (kSPS),
fMCLK = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 1.78 1.59 1.58 0.44 0.43 0.42 0.42 0.42
8192 0.5 2.51 2.19 2.07 0.60 0.59 0.58 0.58 0.58
4096 1 3.41 2.97 2.84 0.82 0.81 0.80 0.80 0.80
2048 2 4.54 3.96 3.76 1.07 1.06 1.05 1.05 1.05
1024 4 5.42 4.74 4.52 1.29 1.28 1.27 1.27 1.27
512 8 8.15 6.91 6.50 1.82 1.81 1.80 1.80 1.80
256 16 13.02 10.33 9.37 2.61 2.56 2.53 2.53 2.53
128 32 23.12 16.45 13.64 4.02 3.73 3.63 3.63 3.63
Table 7-2 Effective Resolution at TA = 25°C
OSR DATA RATE (kSPS),
fMCLK = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 20.4 19.5 18.5 19.4 18.4 17.4 16.4 15.4
8192 0.5 19.9 19.1 18.1 18.9 18.0 17.0 16.0 15.0
4096 1 19.4 18.6 17.7 18.5 17.5 16.5 15.5 14.5
2048 2 19.0 18.2 17.3 18.1 17.1 16.1 15.1 14.1
1024 4 18.8 17.9 17.0 17.8 16.8 15.8 14.8 13.8
512 8 18.2 17.4 16.5 17.3 16.3 15.3 14.3 13.3
256 16 17.5 16.8 16.0 16.8 15.8 14.9 13.9 12.9
128 32 16.7 16.2 15.4 16.2 15.3 14.3 13.3 12.3
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