ZHCSN79 September 2021 ADS131B02-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Programming
- 8.5.1
Serial Interface
- 8.5.1.1 Chip Select (CS)
- 8.5.1.2 Serial Data Clock (SCLK)
- 8.5.1.3 Serial Data Input (DIN)
- 8.5.1.4 Serial Data Output (DOUT)
- 8.5.1.5 Data Ready (DRDY)
- 8.5.1.6 SPI Communication Frames
- 8.5.1.7 SPI Communication Words
- 8.5.1.8 Short SPI Frames
- 8.5.1.9 Communication Cyclic Redundancy Check (CRC)
- 8.5.1.10 SPI Timeout
- 8.5.2 ADC Conversion Data Format
- 8.5.3 Commands
- 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
- 8.5.1
Serial Interface
- 8.6 Register Map
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.6 Clocking
The ADS131B02-Q1 requires a main clock (MCLK) to operate. The main clock to the ADS131B02-Q1 is provided in one of two ways, as shown in Figure 8-3: an external clock on the CLKIN pin or the internal oscillator. The CLK_SEL bit in the CLOCK register selects the according main clock source for the device.
Figure 8-3 Main Clock
Selection Diagram