The DRDY pin is an active-low digital output that indicates when new conversion data are available for readout. Connect the DRDY pin to a digital input on the host to trigger periodic data retrieval in conversion mode.

A high-to-low transition of the DRDY output indicates that new conversion data completed and are ready for readout. The period between DRDY falling edges is the data-rate period. A low level of the DRDY pin indicates that the latest conversion data have not yet been read. DRDY transitions high when the conversion data of the four ADC channels, including those of disabled channels, are shifted out of the device. DRDY stays low if the data read is incomplete, thus indicating that not all ADC data have been retrieved. In case conversion data are not read before the next conversion cycle completes, DRDY transitions high t_w(DRH) ahead of the next DRDY falling edge. See the Section 8.5.4 section for more information about the behavior of DRDY when data are not consistently read. The DRDY high pulse is blocked when new conversions complete while conversion data are read. Therefore, avoid reading ADC data during the time where new conversions complete in order to achieve consistent DRDY behavior.

The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not asserted.