ZHCSMK3B November 2020 – November 2021 ADS131B04-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Programming
- 8.5.1
Serial Interface
- 8.5.1.1 Chip Select (CS)
- 8.5.1.2 Serial Data Clock (SCLK)
- 8.5.1.3 Serial Data Input (DIN)
- 8.5.1.4 Serial Data Output (DOUT)
- 8.5.1.5 Data Ready (DRDY)
- 8.5.1.6 SPI Communication Frames
- 8.5.1.7 SPI Communication Words
- 8.5.1.8 Short SPI Frames
- 8.5.1.9 Communication Cyclic Redundancy Check (CRC)
- 8.5.1.10 SPI Timeout
- 8.5.2 ADC Conversion Data Format
- 8.5.3 Commands
- 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
- 8.5.1
Serial Interface
- 8.6 Register Map
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.5.3.2 RESET (0000 0000 0001 0001)
The RESET command resets the ADC to its register defaults. The command is latched by the device at the end of the frame. A reset occurs immediately after the command is latched. The host must wait for tREGACQ after reset or for the DRDY rising edge before communicating with the device to make sure the registers have assumed their default settings. The device sends an acknowledgment of FF44h when the ADC is properly RESET. The device responds with 0011h if the command word is sent but the frame is not completed and therefore the device is not reset. See the Section 8.4.1.3 section for more information regarding the operation of the reset command. Figure 8-20 illustrates a properly sent RESET command frame.
Figure 8-20 RESET Command
Frame