The ADS131B23-Q1 requires a main clock (MCLK) to operate. As shown in Figure 9-1, the main clock to the ADS131B23-Q1 is provided in one of two ways:

• By the internal 8.192-MHz main oscillator (OSCM) or
• By an external clock on the CLK pin

The CLK_SOURCE bit selects the according main clock source for the device. At device power-up or after device reset, the internal main oscillator is selected as the MCLK source by default.

The modulator clock of the various delta-sigma ADCs is derived from the common main clock. A clock divider divides the main clock frequency (f_MCLK) by a factor of two to create the modulator frequency (f_MOD = f_MCLK / 2) with a duty cycle of 50%.

Before changing the clock source using the CLK_SOURCE bit, disable all ADCs using the respective ADC enable bits or set the device in standby mode to prevent clock glitching during the clock switchover. When switching from an external clock source to the internal main oscillator, keep the external clock running until after the device switched over to the internal main oscillator.

The ADS131B23-Q1 integrates a second internal oscillator, called the diagnostic oscillator (OSCD), which is used for various monitoring and diagnostic functions.