The ADS131B23-Q1 offers four additional GPIO pins (GPIO0A, GPIO1A, GPIO0B, and GPIO1B) that use logic levels based on the AVDD supply. See the Electrical Characteristics table for details regarding the logic high and low levels. The GPIOs offer a multitude of configuration options:

• Configure the individual GPIOs as either digital inputs or digital outputs using the respective GPIOxy_DIR bits (x = 0 or 1, y = A or B).
• Configure the input format of the individual GPIOs for either static logic level or PWM inputs using the respective GPIOxy_FMT bits. In contrast to GPIO0 to GPIO4, the GPIOxy do not offer PWM output capability. Select the appropriate PWM timebase for each GPIO PWM decoder using the GPIOxy_PWM_TB[1:0] bits. The timebase of the source driving the GPIOxy input must be equal to or slower than the timebase of the GPIOxy input decoder, otherwise the logic levels are not correctly decoded. GPIOxy always uses static logic levels when configured as a digital output.

Use the GPOxy_DAT bit to drive a logic high or low level on the respective GPIO pin when GPIOxy is configured as a digital output. The GPIO outputs are push-pull.

The device always reads back the value of the GPIOs and provides the detected logic level in the GPIxy_DAT[1:0] bit fields, regardless if GPIOxy is configured as a digital input or output. See the GPIxy_DAT[1:0] bit field descriptions for details on how the device decodes PWM signals.