The ADS131B23-Q1 implements an SCLK counter that counts the received SCLK pulses within a frame. If the number of received SCLK pulses does not match the number of SCLKs to complete a specific frame, then the SCLK_COUNT_FAULTn flag is set in the following frame. Enable or disable the SCLK counter using the SCLK_COUNTER_EN bit.

The device determines the number of SCLKs expected for a specific SPI frame at the end of the command CRC word. Both the expected number of words to be received on SDI and the words to be transmitted on SDO are considered in the SCLK count calculation. The larger of the two values determines the SCLK count for the frame. For example, the SCLK count in the two frames in Figure 9-35 is (4 × N_{WORD_LENGTH}), while in Figure 9-36 the SCLK count for the frame is (9 × N_{WORD_LENGTH}). The data word length, N_{WORD_LENGTH}, is either 24 or 32, as configured by the WORD_LENGTH bit.

Sending more SCLK pulses than required to complete a frame does not impact the SPI communication, however the SCLK_COUNT_FAULTn does still set in that case to indicate that too many SCLKs were received.

Sending insufficient SCLK pulses to complete a frame does impact the SPI communication in certain situations:

• NULL command: No effect.
• RESET command: Does not execute until sufficient SCLK pulses are provided to clock out the complete output CRC word on SDO.
• LOCK, UNLOCK, RREG commands: Do execute if at least the command and command CRC words are received on SDI.
• WREG command: Does execute if at least the command, command CRC, register data, and register data CRC words are received on SDI.
• DRDYn pin: The DRDYn pin only transitions high after the conversion data word for ADC1B is clocked out on SDO. Otherwise, the device assumes the host did not receive the latest conversion data and the DRDYn pin stays low.