The ADS131B24-Q1 implements an SPI timeout feature that measures the time between the CSn falling and CSn rising edge within a frame. If the CSn rising edge does not occur within the SPI timeout period (t_TIMEOUT) after the CSn falling edge, then the SPI_TIMEOUTn flag is set in the following frame. When a timeout occurs, the rest of the SPI frame on SDI is ignored before the rising edge of CSn. A new SPI transaction starts at the next CSn falling edge. Enable or disable the SPI timeout using the TIMEOUT_EN bit.

If the SPI times out after a complete frame was transmitted on SDI and SDO already, then there is no impact to the SPI communication, however the SPI_TIMEOUTn flag does still set in that case to indicate that the CSn signal was held low for too long.

If the SPI times out before a complete frame is transmitted on SDI and SDO, then there is potential impact to the SPI communication in certain situations:

• NULL command: No effect.
• RESET command: Does not execute until the complete output CRC word is clocked out on SDO before the SPI times out.
• LOCK, UNLOCK, RREG commands: Do execute if at least the command and command CRC words are received on SDI before the SPI times out.
• WREG command: Does execute if at least the command, command CRC, register data, and register data CRC words are received on SDI before the SPI times out.
• DRDYn pin: The DRDYn pin only transitions high after the conversion data word for ADC1B is clocked out on SDO before the SPI times out. Otherwise, the device assumes the host did not receive the latest conversion data and the DRDYn pin stays low.