ZHCSN80
july 2023
ADS131B24-Q1
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Revision History
5
说明(续)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Switching Characteristics
7.8
Timing Diagram
7.9
Typical Characteristics
8
Parameter Measurement Information
8.1
Offset Drift Measurement
8.2
Gain Drift Measurement
8.3
Noise Performance
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Naming Conventions
9.3.2
Precision Voltage References (REFA, REFB)
9.3.3
Clocking (MCLK, OSCM, OSCD)
9.3.4
ADC1y
9.3.4.1
ADC1y Input Multiplexer
9.3.4.2
ADC1y Programmable Gain Amplifier (PGA)
9.3.4.3
ADC1y ΔΣ Modulator
9.3.4.4
ADC1y Digital Filter
9.3.4.5
ADC1y Offset and Gain Calibration
9.3.4.6
ADC1y Conversion Data
9.3.5
ADC2y
9.3.5.1
ADC2y Input Multiplexer
9.3.5.2
ADC2y Programmable Gain Amplifier (PGA)
9.3.5.3
ADC2y ΔΣ Modulator
9.3.5.4
ADC2y Digital Filter
9.3.5.5
ADC2y Offset and Gain Calibration
9.3.5.6
ADC2y Sequencer
9.3.5.7
VCMy Buffers
9.3.5.8
ADC2y Measurement Configurations
9.3.5.9
ADC2y Conversion Data
9.3.6
General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
9.3.6.1
GPIOx PWM Output Configuration
9.3.6.2
GPIOx PWM Input Readback
9.3.7
General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
9.3.8
Monitors and Diagnostics
9.3.8.1
Supply Monitors
9.3.8.2
Clock Monitors
9.3.8.3
Digital Monitors
9.3.8.3.1
Register Map CRC
9.3.8.3.2
Memory Map CRC
9.3.8.3.3
GPIO Readback
9.3.8.4
Communication Monitors
9.3.8.5
Fault Flags and Fault Masking
9.3.8.6
FAULT Pin
9.3.8.7
Diagnostics and Diagnostic Procedure
9.3.8.8
Indicators
9.3.8.9
Conversion and Sequence Counters
9.3.8.10
Supply Voltage Readback
9.3.8.11
Temperature Sensors (TSA, TSB)
9.3.8.12
Test DACs (TDACA, TDACB)
9.3.8.13
Open-Wire Detection
9.3.8.14
Missing Host Detection and MHD Pin
9.3.8.15
Overcurrent Comparators (OCCA, OCCB)
9.3.8.15.1
OCCA and OCCB Pins
9.3.8.15.2
Overcurrent Indication Response Time
9.4
Device Functional Modes
9.4.1
Power-Up and Reset
9.4.1.1
Power-On Reset (POR)
9.4.1.2
RESETn Pin
9.4.1.3
RESET Command
9.4.2
Operating Modes
9.4.2.1
Active Mode
9.4.2.2
Standby Mode
9.4.2.3
Power-Down Mode
9.4.3
ADC Conversion Modes
9.4.3.1
ADC1y Conversion Modes
9.4.3.1.1
Continuous-Conversion Mode
9.4.3.1.2
Single-Shot Conversion Mode
9.4.3.1.3
Global-Chop Mode
9.4.3.1.3.1
Overcurrent Indication Response Time in Global-Chop Mode
9.4.3.2
ADC2y Sequencer Operation and Sequence Modes
9.4.3.2.1
Continuous Sequence Mode
9.4.3.2.2
Single-Shot Sequence Mode
9.4.3.2.3
Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
9.5
Programming
9.5.1
Serial Interface
9.5.1.1
Serial Interface Signals
9.5.1.1.1
Chip Select (CSn)
9.5.1.1.2
Serial Data Clock (SCLK)
9.5.1.1.3
Serial Data Input (SDI)
9.5.1.1.4
Serial Data Output (SDO)
9.5.1.1.5
Data Ready (DRDYn)
9.5.1.2
Serial Interface Communication Structure
9.5.1.2.1
SPI Communication Frames
9.5.1.2.2
SPI Communication Words
9.5.1.2.3
STATUS Word
9.5.1.2.4
Communication Cyclic Redundancy Check (CRC)
9.5.1.2.5
Commands
9.5.1.2.5.1
NULL (0000 0000 0000 0000b)
9.5.1.2.5.2
RESET (0000 0000 0001 0001b)
9.5.1.2.5.3
LOCK (0000 0101 0101 0101b)
9.5.1.2.5.4
UNLOCK (0000 0110 0101 0101b)
9.5.1.2.5.5
WREG (011a aaaa aaa0 0nnnb)
9.5.1.2.5.6
RREG (101a aaaa aaan nnnnb)
9.5.1.2.6
SCLK Counter
9.5.1.2.7
SPI Timeout
9.5.1.2.8
Reading ADC1A, ADC1B, ADC2A, and ADC2B Conversion Data
9.5.1.2.9
DRDYn Pin Behavior
9.6
Register Map
9.6.1
Registers
10
Application and Implementation
10.1
Application Information
10.1.1
Unused Inputs and Outputs
10.1.2
Minimum Interface Connections
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Current Shunt Measurement
10.2.2.2
Battery Pack Voltage Measurement
10.2.2.3
Shunt Temperature Measurement
10.2.2.4
Analog Output Temperature Sensor Measurement
10.2.3
Application Curves
10.3
Power Supply Recommendations
10.3.1
Power-Supply Options
10.3.1.1
Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
10.3.1.2
Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
10.3.1.3
Single Regulated External 5-V Supply (5-V Digital I/O Levels)
10.3.2
Power-Supply Sequencing
10.3.3
Power-Supply Decoupling
10.4
Layout
10.4.1
Layout Guidelines
10.4.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
接收文档更新通知
11.3
支持资源
11.4
Trademarks
11.5
静电放电警告
11.6
术语表
12
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
PHP|48
MPQF051B
散热焊盘机械数据 (封装 | 引脚)
PHP|48
PPTD118C
订购信息
zhcsn80_oa
4
Revision History
DATE
REVISION
NOTES
july 2023
*
Initial Release
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