at TA = 25°C, APWR = 5 V,
DPWR = 5 V, and external clock with fCLK = 8.192 MHz (unless otherwise
noted)
![ADS131B26-Q1 ADC1y
Offset Error Histogram GUID-20221218-SS0I-BQGZ-VPTJ-HGXJWVZSBH8K-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-BQGZ-VPTJ-HGXJWVZSBH8K-low.svg)
32
devices, gain = 8, global-chop disabled, input
referred |
Figure 7-2 ADC1y
Offset Error Histogram![ADS131B26-Q1 ADC1y
Offset Error Histogram GUID-20221218-SS0I-N85V-PGVR-SXBGGS220ZS8-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-N85V-PGVR-SXBGGS220ZS8-low.svg)
32
devices, gain = 8, global-chop enabled, input
referred |
Figure 7-4 ADC1y
Offset Error Histogram![ADS131B26-Q1 ADC1y
Gain Error Histogram GUID-20221222-SS0I-9KDQ-M5F1-JFRCHQKTJCSG-low.svg](/ods/images/ZHCSMK4A/GUID-20221222-SS0I-9KDQ-M5F1-JFRCHQKTJCSG-low.svg)
32
devices, gain = 4, including error of REFy |
Figure 7-6 ADC1y
Gain Error Histogram![ADS131B26-Q1 ADC2y Offset
Error Histogram GUID-20221218-SS0I-RHZN-J9SJ-GRLSDGHSFJWD-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-RHZN-J9SJ-GRLSDGHSFJWD-low.svg)
32
devices, gain = 1, input referred |
Figure 7-8 ADC2y Offset
Error Histogram![ADS131B26-Q1 ADC2y Gain
Error Histogram GUID-20221218-SS0I-LCJT-9HV8-PTKL1HGFBD5W-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-LCJT-9HV8-PTKL1HGFBD5W-low.svg)
32
devices, gain = 1, including error of REFy |
Figure 7-10 ADC2y Gain
Error Histogram![ADS131B26-Q1 ADC3y
Offset Error Histogram GUID-20221218-SS0I-NRNJ-SQCK-2WHNWFSJM4WT-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-NRNJ-SQCK-2WHNWFSJM4WT-low.svg)
32
devices, gain = 1, global-chop disabled, input
referred |
Figure 7-12 ADC3y
Offset Error Histogram![ADS131B26-Q1 ADC3y Offset Error
Histogram GUID-20221218-SS0I-SKXK-BQM0-KKFLCK7H6R52-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-SKXK-BQM0-KKFLCK7H6R52-low.svg)
32
devices, gain = 1, global-chop enabled, input
referred |
Figure 7-14 ADC3y Offset Error
Histogram![ADS131B26-Q1 ADC3y Gain Error
Histogram GUID-20221218-SS0I-1VGS-DMSC-ZTSXFHFGXRPZ-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-1VGS-DMSC-ZTSXFHFGXRPZ-low.svg)
32
devices, gain = 1, including error of REFy |
Figure 7-16 ADC3y Gain Error
Histogram
Figure 7-18 REFy Output Voltage
Histogram
Figure 7-20 OSCM and OSCD Frequency
Histogram![ADS131B26-Q1 OCCy Offset Error
Histogram GUID-20221218-SS0I-MWSP-6SVQ-DJ0LRNQSXVML-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-MWSP-6SVQ-DJ0LRNQSXVML-low.svg)
27
devices, ADC1y gain = 4, input referred |
Figure 7-22 OCCy Offset Error
Histogram![ADS131B26-Q1 OCCy Gain Error
Histogram GUID-20221218-SS0I-MQBL-T0C6-SZQ7GCNMKJTC-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-MQBL-T0C6-SZQ7GCNMKJTC-low.svg)
32
devices, ADC1y gain = 4, including error of REFy |
Figure 7-24 OCCy Gain Error
Histogram
Figure 7-26 Temperature Sensor Output
Voltage Histogram![ADS131B26-Q1 Test DACy Output Voltage
Histogram GUID-20221220-SS0I-BKBR-2MG2-CJGSBG0BPXZM-low.svg](/ods/images/ZHCSMK4A/GUID-20221220-SS0I-BKBR-2MG2-CJGSBG0BPXZM-low.svg)
TDACy output voltage = 9 × VREFy /
40 |
Figure 7-28 Test DACy Output Voltage
Histogram![ADS131B26-Q1 Test DACy Output Voltage
Histogram GUID-20221220-SS0I-X5VJ-SLL3-5DRWMLFFMHTJ-low.svg](/ods/images/ZHCSMK4A/GUID-20221220-SS0I-X5VJ-SLL3-5DRWMLFFMHTJ-low.svg)
TDACy output voltage = –9 × VREFy /
40 |
Figure 7-30 Test DACy Output Voltage
Histogram
Figure 7-32 ADC2y Supply
Voltage Readback Measurement Accuracy
Figure 7-34 Analog GPIO Pin Output
Voltage vs
Sinking Current
Figure 7-36 Digital Pin Output Voltage
vs Sinking Current
Figure 7-38 VCMy Output
Voltage vs Temperature
Figure 7-40 AVDD and IOVDD LDO Output
Voltage vs Temperature![ADS131B26-Q1 Supply Current vs Supply
Voltage GUID-20230501-SS0I-PXRF-BNWG-S9X1J3SQ3HJW-low.svg](/ods/images/ZHCSMK4A/GUID-20230501-SS0I-PXRF-BNWG-S9X1J3SQ3HJW-low.svg)
Active mode, all ADCs enabled and converting |
Figure 7-42 Supply Current vs Supply
Voltage![ADS131B26-Q1 ADC1y
Offset Error vs Temperature GUID-20221218-SS0I-D5FR-1XGW-N9SWG4MK7Z25-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-D5FR-1XGW-N9SWG4MK7Z25-low.svg)
Global-chop disabled, input referred |
Figure 7-3 ADC1y
Offset Error vs Temperature![ADS131B26-Q1 ADC1y
Offset Error vs Temperature GUID-20221218-SS0I-3S5P-HX5S-NJ557LRPX3TQ-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-3S5P-HX5S-NJ557LRPX3TQ-low.svg)
Global-chop enabled, input referred |
Figure 7-5 ADC1y
Offset Error vs Temperature
Figure 7-7 ADC1y
Gain Error vs Temperature
Figure 7-9 ADC2y Offset
Error vs Temperature
Figure 7-11 ADC2y Gain
Error vs Temperature![ADS131B26-Q1 ADC3y Offset Error vs
Temperature GUID-20221218-SS0I-6RDJ-P2PS-GFD5960CCKKF-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-6RDJ-P2PS-GFD5960CCKKF-low.svg)
Global-chop disabled, input referred |
Figure 7-13 ADC3y Offset Error vs
Temperature![ADS131B26-Q1 ADC3y Offset Error vs
Temperature GUID-20221218-SS0I-XMG9-JSJN-VLZR5CDXS2ZX-low.svg](/ods/images/ZHCSMK4A/GUID-20221218-SS0I-XMG9-JSJN-VLZR5CDXS2ZX-low.svg)
Global-chop enabled, input referred |
Figure 7-15 ADC3y Offset Error vs
Temperature
Figure 7-17 ADC3y Gain Error vs
Temperature
Figure 7-19 REFy Output Voltage vs
Temperature
Figure 7-21 OSCM and OSCD Frequency vs
Temperature
Figure 7-23 OCCy Offset Error vs
Temperature
Figure 7-25 OCCy Gain Error vs
Temperature
Figure 7-27 Temperature Sensor
Measurement Error vs Ambient Temperature![ADS131B26-Q1 Test DACy Output Voltage
vs Temperature GUID-20221220-SS0I-H7N7-NM5Q-GRSNMCB0MCWJ-low.svg](/ods/images/ZHCSMK4A/GUID-20221220-SS0I-H7N7-NM5Q-GRSNMCB0MCWJ-low.svg)
TDACy output voltage = 9 × VREFy /
40 |
Figure 7-29 Test DACy Output Voltage
vs Temperature![ADS131B26-Q1 Test DACy Output Voltage
vs Temperature GUID-20221220-SS0I-BPCB-G1SN-9HDTPTTJXXT2-low.svg](/ods/images/ZHCSMK4A/GUID-20221220-SS0I-BPCB-G1SN-9HDTPTTJXXT2-low.svg)
TDACy output voltage = –9 × VREFy /
40 |
Figure 7-31 Test DACy Output Voltage
vs Temperature
Figure 7-33 ADC2y Supply
Voltage Readback Measurement Accuracy
Figure 7-35 Analog GPIO Pin Output
Voltage vs
Sourcing Current
Figure 7-37 Digital Pin Output Voltage
vs Sourcing Current
Figure 7-39 AVDD and IOVDD LDO Output
Voltage Histogram![ADS131B26-Q1 Supply Current vs
Temperature GUID-20230501-SS0I-CNXC-SRGP-KXPM5BFFRQL7-low.svg](/ods/images/ZHCSMK4A/GUID-20230501-SS0I-CNXC-SRGP-KXPM5BFFRQL7-low.svg)
Active mode, all ADCs enabled and converting |
Figure 7-41 Supply Current vs
Temperature