The STATUS_LSB register includes 2-bit conversion and sequence counters for the various ADCs (CONV1y_COUNT[1:0], SEQ2y_COUNT[1:0]).

The conversion counter, CONV1y_COUNT[1:0], increments every time a new conversion on ADC1y completes. Because ADC1A and ADC3A always start converting at the same time when both ADCs are enabled, the CONV1A_COUNT[1:0] indicates the conversion count for ADC3A as well. If ADC1A is disabled, but ADC3A is enabled, then CONV1A_COUNT[1:0] indicates the conversion number for ADC3A. The same is true for ADC1B and ADC3B and CONV1B_COUNT[1:0]. The counter rolls over from 11b to 00b. To reset the counter, disable ADC1y and ADC3y or place the device in standby or power-down mode. The device makes sure that the conversion counter value always matches to the ADC1y and ADC3y conversion results that are output in the same SPI frame.

The sequence counter, SEQ2y_COUNT[1:0], increments every time a new sequence on ADC2y completes. The counter rolls over from 11b to 00b. To reset the counter, disable ADC2y or place the device in standby or power-down mode. The device makes sure that the sequence counter value always matches to the ADC2y conversion step results that are output in the same SPI frame. That means, if a new sequence completes while reading out conversion results from the ADC2y conversion step result registers (SEQxy_STEPx_DATA), the conversion results from the new sequence run are blocked from overwriting the conversion result registers, but are internally buffered. Only after the read command is complete do the buffered conversion results from the new sequence run update the conversion step result registers.