This section provides details about the DRDYn pin behavior in various scenarios.

DRDYn transitions low whenever new conversion data complete on ADC1A or ADC1B, depending on which ADC drives the DRDYn signal as configured in the DRDY_CTRL bit. If DRDYn is low when a new conversion completes on ADC1y, then DRDYn drives high t_w(DRH) before the DRDYn falling edge (see Figure 9-40 and Figure 9-42).

DRDYn transitions high after the conversion data for ADC3B are retrieved on SDO (Figure 9-39). If CSn is driven high before the ADC3B conversion data are retrieved, then DRDYn stays low, indicating that not all conversion data were read (Figure 9-40 and Figure 9-41).

Figure 9-41 shows that the same conversion data can be read multiple times until new conversions complete. The ADC1y conversion counters indicate if the same data were read again or if new data were read.

The device avoids data corruption if new conversions n+1 complete while conversion data n are being read. Conversion data n+1 are held in an internal buffer until the read of conversion data n is complete. In the following frame, conversion data n+1 are loaded into the SDO output buffer. DRDYn does not transition high after conversion data n have been read in this case to indicate that new conversion data n+1 are available for readout (see Figure 9-42).

Figure 9-43 illustrates that conversion data n+1 are lost when the host does not read the data before conversions n+2 complete. The ADC1y conversion counters are helpful in this situation to detect if the host missed reading the intermediate conversion results.

Figure 9-39 DRDYn Pin Behavior: Reading All Conversion Data Before New Conversions Complete

Figure 9-40 DRDYn Pin Behavior: Incomplete Read of Conversion Data Before New Conversions Complete

Figure 9-41 DRDYn Pin Behavior: Incomplete Read of Conversion Data Followed by Complete Read of Same Conversion Data

Figure 9-42 DRDYn Pin Behavior: Reading Conversion Data While New Conversions Complete

Figure 9-43 DRDYn Pin Behavior: Missed Reading Intermediate Conversion Results

Setting the STARTy bit drives the DRDYn pin high at the last SCLK falling edge of the register data CRC word within the SPI frame where the CONVERSION_CTRL register is written. However, the old conversion data can still be read until the new conversions become available. Figure 9-44 shows the device behavior when setting the STARTy bit to abort an ongoing conversion and to restart new conversions while reading out conversion data. Figure 9-45 shows a scenario where new conversions complete while setting the STARTy bit and reading out conversion data.

Figure 9-44 DRDYn Pin Behavior: Setting the STARTy Bit While Reading Conversion Data

Figure 9-45 DRDYn Pin Behavior: Setting the STARTy Bit and Reading Conversion Data While New Conversions Complete