11.1 Power-Up Timing

Before device power up, all digital and analog inputs must be low. At the time of power up, keep all of these signals low until the power supplies have stabilized, as shown in Figure 65.

Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to the CLK pin. Wait for time t_POR, then transmit a reset pulse using either the RESET pin or RESET command to initialize the digital portion of the chip. Issue the reset after t_POR or after the VCAP1 voltage is greater than 1.1 V, whichever time is longer. Note that:

• t_POR is described in Table 22.
• The VCAP1 pin charge time is set by the RC time constant set by the capacitor value on VCAP1; see Figure 28.

After releasing RESET, the configuration registers must be programmed (see the CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h] subsection of the Register Map section for details) to the desired settings. The power-up sequence timing is shown in Table 22.

1. Timing to reset pulse is t_POR or after t_BG, whichever is longer.

2. When using an external clock, t_POR timing does not start until CLK is present and valid.

Figure 65. Power-Up Timing Diagram

11.2 Recommended External Capacitor Values

The ADS131E0x power-up time is set by the time required for the critical voltage nodes to settle to their final values. The analog supplies (AVDD and AVSS), digital supply (DVDD), and internal node voltages (VCAPx pins) must be up and stable when the data converter samples are taken to ensure performance. The combined current sourcing capability of the supplies and size of the bypass capacitors dictate the ramp rate of AVDD, AVSS, and DVDD. The VCAPx voltages are charged internally using the supply voltages. Table 23 lists the internal node voltages, their function, and recommended capacitor values to optimize the power-up time.

11.3 Device Connections for Unipolar Power Supplies

Figure 66 shows the ADS131E0x connected to a unipolar supply. In this example, the analog supply (AVDD) is referenced to the analog ground (AVSS) and the digital supply (DVDD) is referenced to the digital ground (DGND). The ADS131E0x supports an analog supply range of AVDD = 2.7 V to 5.25 V when operated in unipolar supply mode.

NOTE:

Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible.

Figure 66. Unipolar Power Supply Operation

11.4 Device Connections for Bipolar Power Supplies

Figure 67 shows the ADS131E0x connected to a bipolar supply. In this example, the analog supply (AVDD) is referenced to the analog ground (AVSS) and the digital supply (DVDD) is referenced to the digital ground (DGND). The ADS131E0x supports an analog supply range of AVDD and AVSS = ±1.5 V to ±2.5 V when operated in bipolar supply mode.

NOTE:

Place the supply, reference, and VCAP1 to VCAP4 capacitors as close to the package as possible.

Figure 67. Bipolar Power Supply Operation