ZHCS960C June   2012  – January 2017 ADS131E04 , ADS131E06 , ADS131E08

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Electromagnetic Interference (EMI) Filter
      2. 9.3.2  Input Multiplexer
        1. 9.3.2.1 Device Noise Measurements
        2. 9.3.2.2 Test Signals (TestP and TestN)
        3. 9.3.2.3 Temperature Sensor (TempP, TempN)
        4. 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)
      3. 9.3.3  Analog Input
      4. 9.3.4  PGA Settings and Input Range
        1. 9.3.4.1 Input Common-Mode Range
      5. 9.3.5  ΔΣ Modulator
      6. 9.3.6  Clock
      7. 9.3.7  Digital Decimation Filter
      8. 9.3.8  Voltage Reference
      9. 9.3.9  Input Out-of-Range Detection
      10. 9.3.10 General-Purpose Digital I/O (GPIO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
        2. 9.4.1.2 Input Signal Step
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Continuous Conversion Mode
      5. 9.4.5 Data Retrieval
        1. 9.4.5.1 Data Ready (DRDY)
        2. 9.4.5.2 Reading Back Data
        3. 9.4.5.3 Status Word
        4. 9.4.5.4 Readback Length
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multibyte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  OFFSETCAL: Channel Offset Calibration
        8. 9.5.3.8  RDATAC: Start Read Data Continuous Mode
        9. 9.5.3.9  SDATAC: Stop Read Data Continuous Mode
        10. 9.5.3.10 RDATA: Read Data
        11. 9.5.3.11 RREG: Read from Register
        12. 9.5.3.12 WREG: Write to Register
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = xxh]
        2. 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h]
        3. 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = E0h]
        4. 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = 40]
        5. 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]
        6. 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]
        7. 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]
        8. 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]
        9. 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device Up for Basic Data Capture
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 Synchronizing Multiple Devices
        2. 10.1.3.2 Standard Configuration
        3. 10.1.3.3 Daisy-Chain Configuration
      4. 10.1.4 Power Monitoring Specific Applications
      5. 10.1.5 Current Sensing
      6. 10.1.6 Voltage Sensing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Timing
    2. 11.2 Recommended External Capacitor Values
    3. 11.3 Device Connections for Unipolar Power Supplies
    4. 11.4 Device Connections for Bipolar Power Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Parameter Measurement Information

8.1 Noise Measurements

Adjust the data rate and PGA gain to optimize the ADS131E0x noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Increasing the PGA gain reduces the input-referred noise, which is particularly useful when measuring low-level signals. Table 1 summarizes the ADS131E0x noise performance with a 3-V analog power supply. Table 2 summarizes the ADS131E0x noise performance with a 5-V analog power supply. Data are representative of typical noise performance at TA = 25°C. Data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS noise for each reading. For the two highest data rates, noise is limited by the ADC quantization noise and does not have a Gaussian distribution. Table 1 and Table 2 show measurements taken with an internal reference. Data are representative of the ADS131E0x noise performance shown in both effective number of bits (ENOB) and dynamic range when using a low-noise external reference (such as the REF5025). ENOB data in Table 1 and Table 2 are calculated using Equation 1 and dynamic range data in Table 1 and Table 2 are calculated using Equation 2.

Equation 1. ADS131E04 ADS131E06 ADS131E08 eq_ENOB_sbas705.gif
Equation 2. ADS131E04 ADS131E06 ADS131E08 eq_DR_sbas705.gif

Table 1. Input-Referred Noise, 3-V Analog Supply, and 2.4-V Reference

DR BITS
(CONFIG1 Register)		 OUTPUT DATA RATE (kSPS) –3-dB BANDWIDTH (Hz) PGA GAIN
x1 x2 x4 x8 x12
DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB
000 64 16768 74.1 12.31 74.1 12.30 74.0 12.29 74.0 12.29 73.9 12.27
001 32 8384 89.6 14.89 89.6 14.88 89.4 14.85 88.6 14.71 87.6 14.55
010 16 4192 102.8 17.07 102.3 16.99 100.6 16.72 97.1 16.12 94.2 15.65
011 8 2096 108.2 18.0 107.4 17.9 105.2 17.5 101.6 16.9 98.9 16.5
100 4 1048 111.4 18.6 109.4 18.4 107.4 18.1 103.5 17.4 100.5 17.0
101 2 524 114.6 19.1 113.7 19.0 111.4 18.6 107.7 18.0 104.9 17.5
110 1 262 117.7 19.6 116.8 19.5 114.5 19.1 110.7 18.5 108.0 18.0

Table 2. Input-Referred Noise, 5-V Analog Supply, And 4-V Reference

DR BITS
(CONFIG1 Register)		 OUTPUT DATA RATE (kSPS) –3-dB BANDWIDTH (Hz) PGA GAIN
x1 x2 x4 x8 x12
DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB DYNAMIC RANGE (dB) ENOB
000 64 16768 74.7 12.41 74.7 12.41 74.7 12.41 74.7 12.41 74.6 12.39
001 32 8384 90.3 15.01 90.3 15.00 90.2 14.99 89.9 14.93 89.4 14.85
010 16 4192 104.3 17.33 104 17.28 103.1 17.12 100.5 16.70 98.1 16.3
011 8 2096 112.3 18.7 111.6 18.6 109.7 18.3 106.3 17.7 103.8 17.3
100 4 1048 116 19.3 115.2 19.2 113.1 18.8 109.5 18.3 106.9 17.8
101 2 524 119.1 19.8 118.2 19.7 116.2 19.4 112.6 18.8 109.9 18.3
110 1 262 122.1 20.4 121.3 20.2 119.1 19.9 115.6 19.3 112.9 18.8
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