ZHCSEJ3B June   2015  – April 2020 ADS131E08S

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
    1.     电源应用：三相电压和电流连接
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Electromagnetic Interference (EMI) Filter
      2. 9.3.2  Input Multiplexer
        1. 9.3.2.1 Device Noise Measurements
        2. 9.3.2.2 Test Signals (TestP and TestN)
        3. 9.3.2.3 Temperature Sensor (TempP, TempN)
        4. 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)
      3. 9.3.3  Analog Input
      4. 9.3.4  PGA Settings and Input Range
        1. 9.3.4.1 Input Common-Mode Range
      5. 9.3.5  ΔΣ Modulator
      6. 9.3.6  Clock
      7. 9.3.7  Digital Decimation Filter
      8. 9.3.8  Voltage Reference
      9. 9.3.9  Input Out-of-Range Detection
      10. 9.3.10 General-Purpose Digital I/O (GPIO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down
      2. 9.4.2 Reset
      3. 9.4.3 Conversion Mode
        1. 9.4.3.1 START Pin Low-to-High Transition or START Command Sent
        2. 9.4.3.2 Input Signal Step
        3. 9.4.3.3 Continuous Conversion Mode
    5. 9.5 Programming
      1. 9.5.1 SPI Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output (DOUT)
        5. 9.5.1.5 Data Ready (DRDY)
      2. 9.5.2 Data Retrieval
        1. 9.5.2.1 Status Word
        2. 9.5.2.2 Readback Length
        3. 9.5.2.3 Data Format
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  WAKEUP: Exit STANDBY Mode
        2. 9.5.3.2  STANDBY: Enter STANDBY Mode
        3. 9.5.3.3  RESET: Reset Registers to Default Values
        4. 9.5.3.4  START: Start Conversions
        5. 9.5.3.5  STOP: Stop Conversions
        6. 9.5.3.6  OFFSETCAL: Channel Offset Calibration
        7. 9.5.3.7  RDATAC: Start Read Data Continuous Mode
        8. 9.5.3.8  SDATAC: Stop Read Data Continuous Mode
        9. 9.5.3.9  RDATA: Read Data
        10. 9.5.3.10 RREG: Read from Register
        11. 9.5.3.11 WREG: Write to Register
        12. 9.5.3.12 Sending Multibyte Commands
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = D2h]
          1. Table 11. ID: ID Control Register Field Descriptions
        2. 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 94h]
          1. Table 12. CONFIG1: Configuration Register 1 Field Descriptions
        3. 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = 00h]
          1. Table 14. CONFIG2: Configuration Register 2 Field Descriptions
        4. 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = E0h]
          1. Table 15. CONFIG3: Configuration Register 3 Field Descriptions
        5. 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]
          1. Table 16. FAULT: Fault Detect Control Register Field Descriptions
        6. 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]
          1. Table 17. CHnSET: Individual Channel Settings Field Descriptions
        7. 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]
          1. Table 18. FAULT_STATP: Fault Detect Positive Input Status Field Descriptions
        8. 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]
          1. Table 19. FAULT_STATN: Fault Detect Negative Input Status Field Descriptions
        9. 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]
          1. Table 20. GPIO: General-Purpose IO Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Multiple Device Configuration
        1. 10.1.1.1 Synchronizing Multiple Devices
        2. 10.1.1.2 Standard Configuration
        3. 10.1.1.3 Daisy-Chain Configuration
      2. 10.1.2 Power Monitoring Specific Applications
      3. 10.1.3 Current Sensing
      4. 10.1.4 Voltage Sensing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Initialization Set Up
      1. 10.3.1 Setting the Device Up for Basic Data Capture
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Timing
    2. 11.2 Recommended External Capacitor Values
    3. 11.3 Device Connections for Unipolar Power Supplies
    4. 11.4 Device Connections for Bipolar Power Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 支持资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Minimum and maximum specifications apply from TA = –40°C to +105°C. Typical specifications are at TA = 25°C. All specifications are at DVDD = 1.8 V, AVDD = 5 V, AVSS = 0 V, VREF = 4 V, external fCLK = 2.048 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Ci Input capacitance 20 pF
IIB Input bias current PGA output in normal range 5 nA
DC input impedance 200 MΩ
PGA PERFORMANCE
Gain settings 1, 2, 4, 8, 12 V/V
BW Bandwidth See Table 3
ADC PERFORMANCE
DR Data rate fCLK = 2.048 MHz 1 4 64 kSPS
Resolution DR = 1 kSPS, 2 kSPS, 4 kSPS, 8 kSPS, and 16 kSPS 24 Bits
DR = 32 kSPS and 64 kSPS 16
CHANNEL PERFORMANCE (DC Performance)
INL Integral nonlinearity Full-scale, best fit 10 ppm
Dynamic range Data rate = 4 kSPS, gain = 1 116 dB
Gain settings other than 1 See the Noise Measurements section
EO Offset error(1) Gain = 1 –100 –450 –800 µV
Offset error drift(1) 0.2 2.5 µV/°C
EG Gain error Excluding voltage reference error 0.1%
Gain drift Excluding voltage reference drift 3 ppm/°C
Gain match between channels 0.2 % of FS
CHANNEL PERFORMANCE (AC Performance)
CMRR Common-mode rejection ratio fCM = 50 Hz or 60 Hz(2) –110 dB
PSRR Power-supply rejection ratio fPS = 50 Hz or 60 Hz –80 dB
Crosstalk fIN = 50 Hz or 60 Hz –125 –113 dB
SNR Signal-to-noise ratio fIN = 50 Hz or 60 Hz, amplitude = –0.5 dBFS, normalized 108 dB
fIN = 50 Hz or 60 Hz, amplitude = –15 dBFS, normalized 115
THD Total harmonic distortion fIN = 50 Hz or 60 Hz, amplitude = –0.5 dBFS –102 dBc
fIN = 50 Hz or 60 Hz, amplitude = –15 dBFS –107
INTERNAL VOLTAGE REFERENCE
VREF Output voltage(1) TA = 25°C, VREF = 2.4 V, VREF_4V = 0 2.4 V
TA = 25°C, VREF = 4 V, VREF_4V = 1 3.88 4 4.12
Accuracy TA = 25°C ±0.2%
Temperature drift TA = –40°C ≤ TA ≤ 105°C 8 ppm/°C
Power-up time VCAP1 = 470 pF, VREFP = 330 nF, settled to 0.2% 1 ms
INTERNAL OSCILLATOR
Internal oscillator clock frequency 2.048 MHz
Internal oscillator accuracy(1) TA = 25°C ±1%
–40°C ≤ TA ≤ +105°C ±3%
Power-up time 20 µs
Internal oscillator power consumption 120 µW
OPERATIONAL AMPLIFIER
Integrated noise 0.1 Hz to 250 Hz 9 µVRMS
Noise density 2 kHz 120 nV/√Hz
GBP Gain bandwidth product 50-kΩ || 10-pF load 100 kHz
SR Slew rate 50-kΩ || 10-pF load 0.25 V/µs
Load current 50 µA
THD Total harmonic distortion fIN = 100 Hz 70 dB
VCM Common-mode input range AVSS + 0.7 AVDD – 0.3 V
Quiescent current consumption 20 µA
FAULT DETECT AND ALARM
Comparator threshold accuracy ±30 mV
SYSTEM MONITORS
Analog supply reading error 2%
Digital supply reading error 2%
Device wake-up From standby mode 31.25 µs
TEMPERATURE SENSOR
Offset voltage TA = 25°C(3) 144 mV
Temperature coefficient(3) 400 µV/°C
SELF-TEST SIGNAL
Signal frequency fCLK / 221 Hz
fCLK / 220
Signal voltage ±1 mV
±2
Accuracy ±2%
DIGITAL INPUTS AND OUTPUTS
VIH High-level input voltage(1) DVDD = 1.7 V to 1.8 V DVDD – 0.2 V V
DVDD = 1.8 V to 3.6 V 0.8 DVDD DVDD + 0.1 V
VIL Low-level input voltage(1) DVDD = 1.7 V to 1.8 V DGND + 0.2 V
DVDD = 1.8 V to 3.6 V DGND – 0.1 0.2 DVDD V
VOH High-level output voltage(1) IOH = –500 µA 0.9 DVDD V
VOL Low-level output voltage(1) IOL = 500 µA 0.1 DVDD V
IIN Input current 0 V < VDigital_Input < DVDD –10 10 µA
SUPPLY CURRENT (Operational Amplifier Turned Off)
IAVDD Analog supply current AVDD – AVSS = 3 V 5.1 mA
AVDD – AVSS = 5 V 5.8
IDVDD Digital supply current DVDD = 3.3 V 1 mA
DVDD = 1.8 V 0.4
POWER DISSIPATION (8 Channels Powered Up)
Power dissipation Normal mode, AVDD – AVSS = 3 V 16 mW
Standby mode, AVDD – AVSS = 3 V 2
Power-down mode, AVDD – AVSS = 3 V 10 µW
Normal mode, AVDD – AVSS = 5 V(1) 29.7 32.9 mW
Standby mode, AVDD – AVSS = 5 V 4.2
Power-down mode, AVDD – AVSS = 5 V 20 µW
(1) Minimum and maximum values are specified by design and characterization data.
(2) CMRR is measured with a common-mode signal of (AVSS + 0.3 V) to (AVDD – 0.3 V). The values indicated are the minimum of the eight channels.
(3) See the Temperature Sensor (TempP, TempN) section for more information.
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