The ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear phase, finite impulse response (FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is decimated and downsampled, to reduce the rate at which data come out of the modulator (f_MOD) to the output data rate (f_DATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR).

The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. In addition, the TBM bit in the CLOCK registers can be used to enable an even lower OSR setting of 64 for highest speed application. There are nine OSR settings in the ADS131M02-Q1, allowing nine different data rate settings for any given controller clock frequency. Table 8-2 lists the OSR settings and their corresponding output data rates for the nominal CLKIN frequencies mentioned.

The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth results in lower noise whereas higher bandwidth results in higher noise. See Table 7-1 for the noise specifications for various OSR settings.