Current-detect mode is a special mode that is helpful for applications requiring tamper detection when the equipment is in a low-power state. In this mode, the ADS131M06-Q1 collects a configurable number of samples at a nominal data rate of 2.7 kSPS and compares the absolute value of the results to a programmable threshold. If a configurable number of results exceed the threshold, the host is notified via a DRDY falling edge and the device returns to standby mode. Enter current-detect mode by providing a negative pulse on SYNC/RESET with a pulse duration less than t_w(RSL) when in standby mode. Current-detect mode can only be entered from standby mode.

The device uses a limited power operating mode to generate conversions in current-detect mode. The conversion results are only used for comparison by the internal digital threshold comparator and are not accessible by the host. The device uses an internal oscillator that enables the device to capture the data without the use of the external clock input. Do not toggle CLKIN when in current-detect mode to minimize device power consumption. Do not place a capacitor on the REFIN pin if current-detect mode is used. Capacitance on this pin requires time to start up, and the resulting ADC conversions generated during current-detect mode are not valid when the voltage on the REFIN pin is charging.

Current-detect mode is configured in the CFG, THRSHLD_MSB, and THRSHLD_LSB registers. Enable and disable current-detect mode by toggling the CD_EN bit in the CFG register. The THRSHLD_MSB and THRSHLD_LSB registers contain the CD_THRSH[23:0] bits that represent the digital comparator threshold value during current detection.

The number of samples used for current detection are programmed by the CD_LEN[2:0] bits in the CFG register. The number of samples used for current detection range from 128 to 3584.

The programmable values in CD_NUM[2:0] configure the number of samples that must exceed the threshold for a detection to occur. The purpose of requiring multiple samples for detection is to control noisy values that may exceed the threshold, but do not represent a high enough power level to warrant action by the host. In summary, the conversion result must exceed the value programmed in CD_THRSH[23:0] a number of times as represented by the value stored in CD_NUM[2:0].

The device can be configured to notify the host based on any of the results from individual channels, all channels, or any combination of channels. The CD_ALLCH bit in the CFG register determines how many channels are required to exceed the programmed thresholds to trigger a current detection. When the bit is 1, all enabled channels are required to meet the current detection requirements in order for the host to be notified. If the bit is 0, any enabled channel triggers a current detection notification if the requirements are met. Enable and disable channels using the CHn_EN bits in the CLK register to control which combination of channels must meet the requirements to trigger a current-detection notification.

Figure 8-17 illustrates a flow chart depicting the current-detection process on the ADS131M06-Q1.

Figure 8-17 Current-Detect Mode Flow Chart