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ZHCS921A May 2012 – January 2016 ADS4128

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND131R

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	AVDD	–0.3	2.1	V
Supply voltage	DRVDD	–0.3	2.1	V
Voltage	Between AGND and DRGND	–0.3	0.3	V
	Between AVDD to DRVDD (when AVDD leads DRVDD)	0	2.1
	Between DRVDD to AVDD (when DRVDD leads AVDD)	0	2.1
Voltage applied to input pins	INP, INM	–0.3	(1.9) AVDD + 0.3	V
	CLKP, CLKM⁽²⁾, DFS, OE	–0.3	AVDD + 0.3
	RESET, SCLK, SDATA, SEN	–0.3	3.9
Temperature	Operating free-air, T_A	–40	85	°C
	Operating junction, T_J		125	°C
	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP and CLKM is less than |0.3 V|. This setting prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range, unless otherwise noted.

		MIN	TYP	MAX	UNIT
SUPPLIES
AVDD	Analog supply voltage	1.7	1.8	1.9	V
DRVDD	Digital supply voltage	1.7	1.8	1.9	V
ANALOG INPUTS
Differential input voltage range⁽¹⁾			2		V_PP
Input common-mode voltage			V_CM ± 0.05		V
Maximum analog input frequency	With 2-V_PP input amplitude⁽²⁾		400		MHz
Maximum analog input frequency	With 1-V_PP input amplitude⁽²⁾		800		MHz
CLOCK INPUT
Input clock sample rate, low-speed mode	Enabled⁽³⁾	20		80	MSPS
Input clock sample rate, low-speed mode	Disabled⁽³⁾	> 80		200	MSPS
Input clock amplitude differential (V_CLKP – V_CLKM)	Sine wave, ac-coupled	0.2	1.5		V_PP
	LVPECL, ac-coupled		1.6
	LVDS, ac-coupled		0.7
	LVCMOS, single-ended, ac-coupled		1.8		V
Input clock duty cycle	Low-speed mode enabled	40%	50%	60%
Input clock duty cycle	Low-speed mode disabled	35%	50%	65%
DIGITAL OUTPUTS
C_LOAD	Maximum external load capacitance from each output pin to DRGND		5		pF
R_LOAD	Differential load resistance between the LVDS output pairs (LVDS mode)		100		Ω
T_A	Operating free-air temperature	–40		85	°C

(1) With 0-dB gain. See the Fine Gain section in the Detailed Description for relation between input voltage range and gain.

(2) See the Overview section in the Detailed Description.

(3) It is recommended to use these modes to get best performance. These modes can be set using the serial interface only.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS4128	UNIT
		RGZ (VQFN)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	27.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	15.1	°C/W
R_θJB	Junction-to-board thermal resistance	5.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	5.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 1-dB gain, and DDR LVDS interface, unless otherwise noted.
Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. Note that after reset, the device is in 0-dB gain mode.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution				12	Bits
SNR	Signal-to-noise ratio, LVDS	f_IN = 10 MHz		70		dBFS
		f_IN = 70 MHz		70
		f_IN = 100 MHz		69.7
		f_IN = 170 MHz	65.8	69
		f_IN = 300 MHz		68.2
SINAD	Signal-to-noise and distortion ratio, LVDS	f_IN = 10 MHz		69.8		dBFS
		f_IN = 70 MHz		69.2
		f_IN = 100 MHz		69.1
		f_IN = 170 MHz	65.5	68.8
		f_IN = 300 MHz		67
SFDR	Spurious-free dynamic range	f_IN = 10 MHz		87		dBc
		f_IN = 70 MHz		80
		f_IN = 100 MHz		82
		f_IN = 170 MHz	70	85
		f_IN = 300 MHz		74
THD	Total harmonic distortion	f_IN = 10 MHz		84		dBc
		f_IN = 70 MHz		78
		f_IN = 100 MHz		79
		f_IN = 170 MHz	69	83
		f_IN = 300 MHz		73
HD2	Second-harmonic distortion	f_IN = 10 MHz		90		dBc
		f_IN = 70 MHz		84
		f_IN = 100 MHz		83
		f_IN = 170 MHz	70	85
		f_IN = 300 MHz		74
HD3	Third-harmonic distortion	f_IN = 10 MHz		87		dBc
		f_IN = 70 MHz		80
		f_IN = 100 MHz		82
		f_IN = 170 MHz	70	86
		f_IN = 300 MHz		79
	Worst spur (other than second and third harmonics)	f_IN = 10 MHz		93		dBc
		f_IN = 70 MHz		93
		f_IN = 100 MHz		91
		f_IN = 170 MHz	75	90
		f_IN = 300 MHz		88
IMD	Two-tone intermodulation distortion	f₁ = 46 MHz, f₂ = 50 MHz, each tone at –7 dBFS		–85		dBFS
IMD	Two-tone intermodulation distortion	f₁ = 185 MHz, f₂ = 190 MHz, each tone at –7 dBFS		–90		dBFS
	Input overload recovery	Recovery to within 1% (of final value) for 6-dB overload with sine-wave input		1		Clock cycles
PSRR	AC power-supply rejection ratio	For 50-mV_PP signal on AVDD supply, up to 10 MHz		> 30		dB
ENOB	Effective number of bits	f_IN = 170 MHz		11.2		LSBs
DNL	Differential nonlinearity	f_IN = 170 MHz	–0.95	±0.2	1.6	LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz		±0.5	±5	LSBs

7.6 Electrical Characteristics: General

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and 0-dB gain, unless otherwise noted.
Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Differential input voltage range			2		V_PP
	Differential input resistance (at dc); see Figure 47			> 1		MΩ
	Differential input capacitance; see Figure 48			4		pF
	Analog input bandwidth			550		MHz
	Analog input common-mode current (per input pin)			0.6		µA/MSPS
VCM	Common-mode output voltage			0.95		V
	VCM output current capability			4		mA
DC ACCURACY
	Offset error		–15	2.5	15	mV
	Temperature coefficient of offset error			0.003		mV/°C
E_GREF	Gain error as a result of internal reference inaccuracy alone		–2		2	%FS
E_GCHAN	Gain error of channel alone			–0.2	±1	%FS
	Temperature coefficient of E_GCHAN			0.001		Δ%/°C
POWER SUPPLY
IAVDD	Analog supply current			85	113	mA
IDRVDD⁽²⁾	Output buffer supply current, LVDS interface with 100-Ω external termination	Low LVDS swing (200 mV)		43		mA
		Standard LVDS swing (350 mV)		55	72
	Output buffer supply current⁽²⁾⁽¹⁾ CMOS interface	8-pF external load capacitance f_IN = 2.5 MHz		33
	Analog power			153		mW
	Digital power, LVDS interface	Low LVDS swing (200 mV)		77		mW
	Digital power, CMOS interface⁽¹⁾	8-pF external load capacitance f_IN = 2.5 MHz		59		mW
	Global power-down			10	25	mW
	Standby			185		mW

(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on the output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Device Functional Modes).

(2) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF.

7.7 Digital Characteristics

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, and 50% clock duty cycle, unless otherwise noted.
Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)
V_IH	High-level input voltage	RESET, SCLK, SDATA, and SEN support 1.8-V and 3.3-V CMOS logic levels	1.3			V
V_IH	High-level input voltage	OE only supports 1.8-V CMOS logic levels	1.3			V
V_IL	Low-level input voltage	RESET, SCLK, SDATA, and SEN support 1.8-V and 3.3-V CMOS logic levels			0.4	V
V_IL	Low-level input voltage	OE only supports 1.8-V CMOS logic levels			0.4	V
I_IH	High-level input current, SDATA and SCLK⁽¹⁾	V_HIGH = 1.8 V		10		µA
I_IH	High-level input current, SEN	V_HIGH = 1.8 V		0		µA
I_IL	Low-level input, SDATA and SCLK	V_LOW = 0 V		0		µA
I_IL	Low-level input, SEN	V_LOW = 0 V		10		µA
DIGITAL OUTPUTS (CMOS INTERFACE: D0 to D11, OVR_SDOUT)
V_OH	High-level output voltage		DRVDD – 0.1	DRVDD		V
V_OL	Low-level output voltage			0	0.1	V
DIGITAL OUTPUTS (LVDS INTERFACE: DA0P and DA0M to DA11P and DA11M, DB0P and DB0M to DB11P and DB11M, CLKOUTP and CLKOUTM)
V_ODH	High-level output voltage⁽²⁾	Standard-swing LVDS	270	350	430	mV
V_ODH	High-level output voltage⁽²⁾	Low-swing LVDS		200		mV
V_ODL	Low-level output voltage⁽²⁾	Standard-swing LVDS	–430	–350	–270	mV
V_ODL	Low-level output voltage⁽²⁾	Low-swing LVDS		–200		mV
V_OCM	Output common-mode voltage		0.85	1.05	1.25	V

(1) SDATA and SCLK have an internal 180-kΩ pull-down resistor.

(2) With an external 100-Ω termination.

7.8 Timing Requirements: LVDS and CMOS Modes⁽¹⁾

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock,
C_LOAD = 5 pF⁽²⁾, and R_LOAD = 100 Ω⁽³⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.

			MIN	NOM	MAX	UNIT
t_A	Aperture delay		0.6	0.8	1.2	ns
	Aperture delay variation	Between two devices at the same temperature and DRVDD supply		±100		ps
t_J	Aperture jitter			100		f_S rms
	Wakeup time	Time to valid data after coming out of STANDBY mode		5	25	µs
	Wakeup time	Time to valid data after coming out of PDN GLOBAL mode		100	500	µs
	ADC latency⁽⁸⁾	Low-latency mode (default after reset)		10		Clock cycles
		Low-latency mode disabled (gain enabled, offset correction disabled)		16
		Low-latency mode disabled (gain and offset correction enabled)		17
DDR LVDS MODE⁽⁴⁾⁽⁵⁾
t_SU	Data setup time⁽³⁾	Data valid⁽⁶⁾ to zero-crossing of CLKOUTP	1.05	1.55		ns
t_H	Data hold time⁽³⁾	Zero-crossing of CLKOUTP to data becoming invalid⁽⁶⁾	0.35	0.6		ns
t_PDI	Clock propagation delay	Input clock rising edge crossover to output clock rising edge crossover 1 MSPS ≤ sampling frequency ≤ 200 MSPS	3	4.2	5.4	ns
	Variation of t_PDI	Between two devices at the same temperature and DRVDD supply		±0.6		ns
	LVDS bit clock duty cycle	Duty cycle of differential clock, (CLKOUTP – CLKOUTM) 1 MSPS ≤ sampling frequency ≤ 200 MSPS	42%	48%	54%
t_RISE, t_FALL	Data rising time, Data falling time	Rising time measured from –100 mV to 100 mV Falling time measured from 100 mV to –100 mV 1 MSPS ≤ sampling frequency ≤ 200 MSPS		0.14		ns
t_CLKRISE, t_CLKFALL	Output clock rising time, Output clock falling time	Rising time measured from –100 mV to 100 mV Falling time measured from 100 mV to –100 mV 1 MSPS ≤ sampling frequency ≤ 200 MSPS		0.14		ns
t_OE	Output enable (OE) to data delay	Time to valid data after OE becomes active		50	100	ns
PARALLEL CMOS MODE⁽⁷⁾
t_START	Input clock to data delay	Input clock rising edge crossover to start of data valid⁽⁶⁾			–0.3	ns
t_DV	Data valid time	Time interval of valid data⁽⁶⁾	3.5	4.2		ns
t_PDI	Clock propagation delay	Input clock rising edge crossover to output clock rising edge crossover 1 MSPS ≤ sampling frequency ≤ 200 MSPS	4	5.5	7	ns
	Output clock duty cycle	Duty cycle of output clock, CLKOUT 1 MSPS ≤ sampling frequency ≤ 200 MSPS		47%
t_RISE, t_FALL	Data rising time, Data falling time	Rising time measured from 20% to 80% of DRVDD Falling time measured from 80% to 20% of DRVDD 1 ≤ sampling frequency ≤ 200 MSPS		0.35		ns
t_CLKRISE, t_CLKFALL	Output clock rising time, Output clock falling time	Rising time measured from 20% to 80% of DRVDD Falling time measured from 80% to 20% of DRVDD 1 ≤ sampling frequency ≤ 200 MSPS		0.35		ns
t_OE	Output enable (OE) to data delay	Time to valid data after OE becomes active		20	40	ns

(1) Timing parameters are ensured by design and characterization but are not production tested.

(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.

(3) R_LOAD is the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(5) The LVDS timings are unchanged for low latency disabled and enabled.

(6) Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V.

(7) Low-latency mode enabled.

(8) At higher frequencies, t_PDI is greater than one clock period and overall latency = ADC latency + 1.

7.9 Reset Timing Requirements

Typical values are at 25°C and minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, unless otherwise noted.

			MIN	MAX	UNIT
t₁	Power-on delay	Delay from power-up of AVDD and DRVDD to RESET pulse active	1		ms
t₂	Reset pulse width	Pulse width of active RESET signal that resets the serial registers	10		ns
t₂	Reset pulse width			1⁽¹⁾	µs
t₃		Delay from RESET disable to SEN active	100		ns

(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1 µs, the device can enter the parallel configuration mode briefly and then return back to serial interface mode.

Table 1. LVDS Timing Across Sampling Frequencies

SAMPLING FREQUENCY (MSPS)	SETUP TIME (ns)			HOLD TIME (ns)
SAMPLING FREQUENCY (MSPS)	MIN	TYP	MAX	MIN	TYP	MAX
200	1.05	1.55	—	0.35	0.6	—
185	1.1	1.7	—	0.35	0.6	—
160	1.6	2.1	—	0.35	0.6	—
125	2.3	3	—	0.35	0.6	—
80	4.5	5.2	—	0.35	0.6	—

Table 2. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)

SAMPLING FREQUENCY (MSPS)	TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
	t_SETUP (ns)			t_HOLD (ns)			t_PDI (ns)
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
200	1.6	2.2	—	1.8	2.5	—	4	5.5	7
185	1.8	2.4	—	1.9	2.7	—	4	5.5	7
160	2.3	2.9	—	2.2	3	—	4	5.5	7
125	3.1	3.7	—	3.2	4	—	4	5.5	7
80	5.4	6	—	5.4	6	—	4	5.5	7

Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)

SAMPLING FREQUENCY (MSPS)	TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
	t_SETUP (ns)			t_HOLD (ns)			t_PDI (ns)
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
200	1	1.6	—	2	2.8	—	4	5.5	7
185	1.3	2	—	2.2	3	—	4	5.5	7
160	1.8	2.5	—	2.5	3.3	—	4	5.5	7
125	2.5	3.2	—	3.5	4.3	—	4	5.5	7
80	4.8	5.5	—	5.7	6.5	—	4	5.5	7

Table 4. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)

SAMPLING FREQUENCY (MSPS)	TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
	t_START (ns)			t_DV (ns)
	MIN	TYP	MAX	MIN	TYP	MAX
200	—	—	–0.3	3.5	4.2	—
185	—	—	–1	3.9	4.5	—
170	—	—	–1.5	4.3	5	—

Table 5. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)

SAMPLING FREQUENCY (MSPS)	TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
	t_START (ns)			t_DV (ns)
	MIN	TYP	MAX	MIN	TYP	MAX
200	—	—	0.3	3.5	4.2	—
185	—	—	0	3.9	4.5	—
170	—	—	–1.3	4.3	5	—

ADC latency in low-latency mode. At higher sampling frequencies, t_DPI is greater than one clock cycle which then makes the overall latency = ADC latency + 1.

E = Even bits (D0, D2, D4, and so on). O = Odd bits (D1, D3, D5, and so on).

Figure 1. Latency Diagram

Dn = bits D0, D2, D4, and so on. Dn + 1 = bits D1, D3, D5, and so on.

Figure 2. LVDS Mode Timing

Dn = bits D0, D1, D2, and so forth.

Figure 3. CMOS Mode Timing

With external 100-Ω termination.

Figure 4. LVDS Output Voltage Levels

The OVR_SDOUT pin functions as OVR (READOUT = 0).

The OVR_SDOUT pin functions as a serial readout (READOUT = 1).

Figure 5. Serial Readout Timing Diagram

A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high.

Figure 6. Reset Timing Diagram

Figure 7. Serial Interface Timing

7.10 Typical Characteristics

At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.