8.3.1 Analog Input

The analog input pins have analog buffers (running off the AVDD_BUF supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (10-kΩ dc resistance and 3.5-pF input capacitance). The buffer helps to isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easy when compared to an ADC without the buffer.

The input common-mode is set internally using a 5-kΩ resistor from each input pin to 1.7 V, so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.375 V) and (VCM – 0.375 V), resulting in a 1.5-V_PP differential input swing.

The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pins to the sampled voltage). Figure 54 shows an equivalent circuit for the analog input.

1. C_EQ refers to the equivalent input capacitance of the buffer = 4 pF.

2. R_EQ refers to the R_EQ buffer = 10 Ω.

3. This equivalent circuit is an approximation and valid for frequencies less than 700 MHz.

Figure 54. Analog Input Equivalent Circuit3

8.3.2 Clock Input

The ADS41Bx9 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 55 shows an equivalent circuit for the input clock.

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 55. Input Clock Equivalent Circuit

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 56. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, using a clock source with very low jitter is recommended. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 57 shows a differential circuit.

Figure 56. Single-Ended Clock Driving Circuit

Figure 57. Differential Clock Driving Circuit

8.3.3 Gain for SFDR, SNR Trade-Off

The ADS41Bx9 includes gain settings that can be used to get improved SFDR performance. The gain is programmable from 0 dB to 3.5 dB (in 0.5-dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 1.

The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.

After a reset, the gain is enabled with 0dB gain setting. For other gain settings, program the GAIN register bits.

8.3.4 Offset Correction

The ADS41Bx9 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the EN OFFSET CORR serial register bit. When enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 2.

After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. When frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset.

After a reset, the offset correction is disabled. To use offset correction set EN OFFSET CORR to 1 and program the required time constant. Figure 58 shows the time response of the offset correction algorithm after it is enabled.

Figure 58. Time Response of Offset Correction

8.3.5 Digital Output Information

The ADS41Bx9 provides either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data.

8.3.5.2 DDR LVDS Outputs

In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as illustrated in Figure 59 and Figure 60.

Figure 59. ADS41B29 LVDS Data Outputs

Figure 60. ADS41B49 LVDS Data Outputs

Even data bits (D0, D2, D4, and so forth) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, and so forth) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 61.

Figure 61. DDR LVDS Interface

8.3.5.3 LVDS Output Data and Clock Buffers

The equivalent circuit of each LVDS output buffer is shown in Figure 62. After reset, the buffer presents an output impedance of 100Ω to match with the external 100-Ω termination.

The V_DIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The V_DIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a
100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, signal integrity is improved.

NOTE: Use the default buffer strength to match 100-Ω external termination (R_OUT = 100 Ω). To match with a 50-Ω external termination, set the LVDS STRENGTH bit (R_OUT = 50 Ω).

Figure 62. LVDS Buffer Equivalent Circuit

8.3.5.4 Parallel CMOS Interface

In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 63 depicts the CMOS output interface.

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window (even at 250 MSPS) is provided so the data outputs have minimal load capacitance. Using short traces (one to two inches or 2.54 cm to 5.08 cm) terminated with less than 5-pF load capacitance is recommended; see Figure 64.

For sampling frequencies greater than 200 MSPS, using an external clock to capture data is recommended. The delay from input clock to output data and the data valid times are specified for higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture data.

Figure 63. CMOS Output Interface

Figure 64. Using the CMOS Data Outputs

8.4.1 Device Configuration

The ADS41Bx9 have several modes that can be configured using a serial programming interface, as described in Table 3, Table 4, and Table 5. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).

When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have any alternative functions. Keep SEN tied high and SCLK tied low on the board.

A simple diagram to configure DFS pin is shown in Figure 65.

Figure 65. Simplified Diagram to Configure the DFS Pin

8.4.2 Power-Down

The ADS41Bx9 has three power-down modes: power-down global, standby, and output buffer disable.

8.5.1 Serial Interface

The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20 MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle.

8.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways:

1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10 ns), as shown in Figure 66; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 0x00) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

Figure 66. Serial Interface Timing

Table 6. Serial Interface Timing Characteristics⁽²⁾⁽¹⁾

		MIN	TYP	MAX	UNIT
fSCLK	SCLK frequency (equal to 1 / tSCLK)	> dc		20	MHz
tSLOADS	SEN to SCLK setup time	25			ns
tSLOADH	SCLK to SEN hold time	25			ns
tDSU	SDATA setup time	25			ns
tDH	SDATA hold time	25			ns

(1) Typical values are at 25°C, minimum and maximum values for the ADS41B49 are specified across the ambient temperature range of
T_{A, MIN} = –40°C to T_{A, MAX} = 105°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

(2) Typical values are at 25°C, minimum and maximum values for the ADS41B29 are specified across the ambient temperature range of
T_{A, MIN} = –40°C to T_{A, MAX} = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

8.5.2 Serial Register Readout

The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:

1. Set the READOUT register bit to 1. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of the register at address 0 cannot be read in the register readout mode.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read.
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.

Figure 67 shows the process of reading out register contents on the OVR_SDOUT pin, using register 43h as example.

1. The OVR_SDOUT pin functions as OVR (READOUT = 0).

2. The OVR_SDOUT pin functions as a serial readout (READOUT = 1).

Figure 67. Serial Readout Timing Diagram

8.6.1 Serial Register Map

Table 7 summarizes the functions supported by the serial interface.