In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as Figure 8-24 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. It is recommended to minimize the load capacitance of the data and clock output pins by using short traces to the receiver. Furthermore, match the output data and clock traces to minimize the skew between them.

Figure 8-24 CMOS Outputs