The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 1. Quantinization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.

Equation 1.

SNR limitation is a result of sample clock jitter and can be calculated by Equation 2

Equation 2.

The total clock jitter (T_Jitter) has three components: the internal aperture jitter (85 f_s for the device) is set by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. T_Jitter can be calculated by Equation 3:

Equation 3.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improved ADC aperture jitter. The device has a 74.1-dBFS thermal noise and an 85-f_S internal aperture jitter. The SNR value depends on the amount of external jitter for different input frequencies, as shown in Figure.

Figure 9-2 SNR versus Input Frequency and External Clock Jitter