ZHCS114E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | RESET | READOUT |
| Bits[7:2] | Always write 0 |
| Bit 1 | RESET: Software reset applied |
| This bit resets all internal registers to the default values and self-clears to 0 (default = 1). | |
| Bit 0 | READOUT: Serial readout |
| This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the SDOUT pin is placed in high-impedance state. 1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic levels running from the DRVDD supply. See the Serial Register Readout section. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LVDS SWING | 0 | 0 | |||||
| Bits[7:2] | LVDS SWING: LVDS swing programmability |
| These bits program the LVDS swing. Set the EN LVDS SWING bit to 1 before programming swing. 000000 = Default LVDS swing; ±350 mV with external 100-Ω termination 011011 = LVDS swing increases to ±410 mV 110010 = LVDS swing increases to ±465mV 010100 = LVDS swing increases to ±570 mV 111110 = LVDS swing decreases to ±200 mV 001111 = LVDS swing decreases to ±125mV | |
| Bits[1:0] | Always write 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | HIGH PERF MODE | |
| Bits[7:2] | Always write 0 |
| Bits[1:0] | HIGH PERF MODE: High-performance mode |
| 00 = Default performance 01 = Do not use 10 = Do not use 11 = Obtain best performance across sample clock and input signal frequencies |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH A GAIN | 0 | CH A TEST PATTERNS | |||||
| Bits[7:4] | CH A GAIN: Channel A gain programmability | ||
| These bits set the gain programmability in 0.5-dB steps for channel A. | |||
| 0000 = 0-dB gain (default after reset) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain | |||
| Bit 3 | Always write 0 | ||
| Bits[2:0] | CH A TEST PATTERNS: Channel A data capture | ||
| These bits verify data capture for channel A. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern. For the ADS424x, output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101. For the ADS422x, the output data D[11:0] are an alternating sequence of 101010101010 and 010101010101. 100 = Outputs digital ramp. For the ADS424x, output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383. For the ADS422x, output data increment by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095. 101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern 110 = Unused 111 = Unused | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | DATA FORMAT | 0 | 0 | 0 | |
| Bits[7:5] | Always write 0 | ||
| Bits[4:3] | DATA FORMAT: Data format selection | ||
| 00 = Twos complement 01 = Twos complement 10 = Twos complement 11 = Offset binary | |||
| Bits[2:0] | Always write 0 | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH B GAIN | 0 | CH B TEST PATTERNS | |||||
| Bits[7:4] | CH B GAIN: Channel B gain programmability | ||
| These bits set the gain programmability in 0.5-dB steps for channel B. | |||
| 0000 = 0-dB gain (default after reset) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain | |||
| Bit 3 | Always write 0 | ||
| Bits[2:0] | CH B TEST PATTERNS: Channel B data capture | ||
| These bits verify data capture for channel B. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern. For the ADS424x, output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101. For the ADS422x, the output data D[11:0] are an alternating sequence of 101010101010 and 010101010101. 100 = Outputs digital ramp. For the ADS424x, output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383. For the ADS422x, output data increment by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095. 101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern 110 = Unused 111 = Unused | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | ENABLE OFFSET CORR | 0 | 0 | 0 | 0 | 0 |
| Bits[7:6] | Always write 0 |
| Bit 5 | ENABLE OFFSET CORR: Offset correction setting |
| This bit enables the offset correction. 0 = Offset correction disabled 1 = Offset correction enabled | |
| Bits[4:0] | Always write 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | CUSTOM PATTERN D13 | CUSTOM PATTERN D12 | CUSTOM PATTERN D11 | CUSTOM PATTERN D10 | CUSTOM PATTERN D9 | CUSTOM PATTERN D8 |
| Bits[7:6] | Always write 0 |
| Bits[5:0] | CUSTOM PATTERN D[13:8] |
| These are the six upper bits of the custom pattern available at the output instead of ADC data. Note that for the ADS424x, the custom pattern is 14-bit. The ADS422x custom pattern is 12-bit. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CUSTOM PATTERN D7 | CUSTOM PATTERN D6 | CUSTOM PATTERN D5 | CUSTOM PATTERN D4 | CUSTOM PATTERN D3 | CUSTOM PATTERN D2 | CUSTOM PATTERN D1 | CUSTOM PATTERN D0 |
| Bits[7:0] | CUSTOM PATTERN D[7:0] |
| These are the eight upper bits of the custom pattern available at the output instead of ADC data. Note that for the ADS424x, the custom pattern is 14-bit. The ADS422x custom pattern is 12-bit; use the CUSTOM PATTERN D[13:2] register bits. |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LVDS CMOS | CMOS CLKOUT STRENGTH | 0 | 0 | DIS OBUF | |||
| Bits[7:6] | LVDS CMOS: Interface selection |
| These bits select the interface. 00 = DDR LVDS interface 01 = DDR LVDS interface 10 = DDR LVDS interface 11 = Parallel CMOS interface | |
| Bits[5:4] | CMOS CLKOUT STRENGTH |
| These bits control the strength of the CMOS output clock. 00 = Maximum strength (recommended) 01 = Medium strength 10 = Low strength 11 = Very low strength | |
| Bits[3:2] | Always write 0 |
| Bits[1:0] | DIS OBUF |
| These bits power down data and clock output buffers for both the CMOS and LVDS output interface. When powered down, the output buffers are in 3-state. 00 = Default 01 = Power-down data output buffers for channel B 10 = Power-down data output buffers for channel A 11 = Power-down data output buffers for both channels as well as the clock output buffer |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLKOUT FALL POSN | CLKOUT RISE POSN | EN DIGITAL | 0 | 0 | 0 | ||
| Bits[7:6] | CLKOUT FALL POSN |
| In LVDS mode: 00 = Default 01 = The falling edge of the output clock advances by 450 ps 10 = The falling edge of the output clock advances by 150 ps 11 = The falling edge of the output clock is delayed by 550 ps In CMOS mode: 00 = Default 01 = The falling edge of the output clock is delayed by 150 ps 10 = Do not use 11 = The falling edge of the output clock advances by 100 ps | |
| Bits[5:6] | CLKOUT RISE POSN |
| In LVDS mode: 00 = Default 01 = The rising edge of the output clock advances by 450 ps 10 = The rising edge of the output clock advances by 150 ps 11 = The rising edge of the output clock is delayed by 250 ps In CMOS mode: 00 = Default 01 = The rising edge of the output clock is delayed by 150 ps 10 = Do not use 11 = The rising edge of the output clock advances by 100 ps | |
| Bit 3 | EN DIGITAL: Digital function enable |
| 0 = All digital functions disabled 1 = All digital functions (such as test patterns, gain, and offset correction) enabled | |
| Bits[2:0] | Always write 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STBY | LVDS CLKOUT STRENGTH | LVDS DATA STRENGTH | 0 | 0 | PDN GLOBAL | 0 | 0 |
| Bit 7 | STBY: Standby setting | ||
| 0 = Normal operation 1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50 µs). | |||
| Bit 6 | LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting | ||
| 0 = LVDS output clock buffer at default strength to be used with 100-Ω external termination 1 = LVDS output clock buffer has double strength to be used with 50-Ω external termination | |||
| Bit 5 | LVDS DATA STRENGTH | ||
| 0 = All LVDS data buffers at default strength to be used with 100-Ω external termination 1 = All LVDS data buffers have double strength to be used with 50-Ω external termination | |||
| Bits[4:3] | Always write 0 | ||
| Bit 2 | PDN GLOBAL | ||
| 0 = Normal operation 1 = Total power down; all ADC channels, internal references, and output buffers are powered down. Wakeup time from this mode is slow (typically 100 µs). | |||
| Bits[1:0] | Always write 0 | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | HIGH FREQ MODE CH B |
| Bits[7:1] | Always write 0 | ||
| Bit 0 | HIGH FREQ MODE CH B: High-frequency mode for channel B | ||
| 0 = Default 1 = Use this mode for high input frequencies | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | HIGH FREQ MODE CH A |
| Bits[7:1] | Always write 0 | ||
| Bit 0 | HIGH FREQ MODE CH A: High-frequency mode for channel A | ||
| 0 = Default 1 = Use this mode for high input frequencies | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH A OFFSET PEDESTAL | 0 | 0 | |||||
| Bits[7:2] | CH A OFFSET PEDESTAL: Channel A offset pedestal selection | ||
| When the offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A pedestal can be added to the final converged value by programming these bits. See the Offset Correction section. Channels can be independently programmed for different offset pedestals by choosing the relevant register address. For the ADS424x, the pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+32 by adding pedestal D7-D2. For the ADS422x, the pedestal ranges from –8 to +7, so the output code can vary from midcode-8 to midcode+7 by adding pedestal D7-D4. | |||
| ADS422x (Program Bits D[7:4]) | ADS424x (Program Bits D[7:2]) | ||
| 0111 = Midcode+7 0110 = Midcode+6 0101 = Midcode+5 … 0000 = Midcode 1111 = Midcode-1 1110 = Midcode-2 1101 = Midcode-3 … 1000 = Midcode-8 | 011111 = Midcode+31 011110 = Midcode+30 011101 = Midcode+29 … 000000 = Midcode 111111 = Midcode-1 111110 = Midcode-2 111101 = Midcode-3 … 100000 = Midcode-32 | ||
| Bits[1:0] | Always write 0 | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CH B OFFSET PEDESTAL | 0 | 0 | |||||
| Bits[7:2] | CH B OFFSET PEDESTAL: Channel B offset pedestal selection | |
| When offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A pedestal can be added to the final converged value by programming these bits; see the Offset Correction section. Channels can be independently programmed for different offset pedestals by choosing the relevant register address. For the ADS424x, the pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+32 by adding pedestal D[7:2]. For the ADS422x, the pedestal ranges from –8 to +7, so the output code can vary from midcode-8 to midcode+7 by adding pedestal D[7:4]. | ||
| ADS422x (Program Bits D[7:4]) | ADS424x (Program Bits D[7:2]) | |
| 0111 = Midcode+7 0110 = Midcode+6 0101 = Midcode+5 … 0000 = Midcode 1111 = Midcode-1 1110 = Midcode-2 1101 = Midcode-3 … 1000 = Midcode-8 | 011111 = Midcode+31 011110 = Midcode+30 011101 = Midcode+29 … 000000 = Midcode 111111 = Midcode-1 111110 = Midcode-2 111101 = Midcode-3 … 100000 = Midcode-32 | |
| Bits[1:0] | Always write 0 | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FREEZE OFFSET CORR | 0 | OFFSET CORR TIME CONSTANT | 0 | 0 | |||
| Bit 7 | FREEZE OFFSET CORR: Freeze offset correction setting | |
| This bit sets the freeze offset correction estimation. 0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set) 1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen, the last estimated value is used for offset correction of every clock cycle. See the Offset Correction section. | ||
| Bit 6 | Always write 0 | |
| Bits[5:2] | OFFSET CORR TIME CONSTANT | |
| The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction section. | ||
| Bits[1:0] | Always write 0 | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | LOW SPEED MODE CH B |
| Bits[7:1] | Always write 0 |
| Bit 0 | LOW SPEED MODE CH B: Channel B low-speed mode enable |
| This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to 1 before using this bit. 0 = Low-speed mode is disabled for channel B 1 = Low-speed mode is enabled for channel B |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | EN LOW SPEED MODE | 0 | 0 | 0 | 0 |
| Bits[7:5] | Always write 0 |
| Bit 4 | EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits (ADS42x5 and ADS42x6 only) |
| This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW SPEED MODE CH A register bits. 0 = Low-speed mode is disabled 1 = Low-speed mode is controlled by serial register bits | |
| Bits[3:0] | Always write 0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | EN LVDS SWING | |
| Bits[7:2] | Always write 0 |
| Bits[1:0] | EN LVDS SWING: LVDS swing enable |
| These bits enable LVDS swing control using the LVDS SWING register bits. 00 = LVDS swing control using the LVDS SWING register bits is disabled 01 = Do not use 10 = Do not use 11 = LVDS swing control using the LVDS SWING register bits is enabled |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | LOW SPEED MODE CH A | 0 | 0 | 0 |
| Bits[7:4] | Always write 0 |
| Bit 3 | LOW SPEED MODE CH A: Channel A low-speed mode enable |
| This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to 1 before using this bit. 0 = Low-speed mode is disabled for channel A 1 = Low-speed mode is enabled for channel A | |
| Bits[2:0] | Always write 0 |