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ZHCS114E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RGC|64
- MPQF125F

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND123N

订购信息

7.11 Reset Timing (Only When Serial Interface Is Used)

See the Serial Register Readout section.

PARAMETER		CONDITIONS	MIN	MAX	UNIT
t₁	Power-on delay	Delay from AVDD and DRVDD power-up to active RESET pulse	1		ms
t₂	Reset pulse width	Active RESET signal pulse width	10		ns
t₂	Reset pulse width	Active RESET signal pulse width		1	µs
t₃	Register write delay	Delay from RESET disable to SEN active	100		ns

(1) Typical values at 25°C; minimum and maximum values across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, unless otherwise noted.

Table 7-1 LVDS Timings at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS)	SETUP TIME (ns)			HOLD TIME (ns)			t_PDI, CLOCK PROPAGATION DELAY (ns)
SAMPLING FREQUENCY (MSPS)	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
65	5.9	6.6		0.35	0.6		5	6.1	7.5
80	4.5	5.2		0.35	0.6		5	6.1	7.5
105	3.1	3.6		0.35	0.6		5	6.1	7.5
125	2.3	2.9		0.35	0.6		5	6.1	7.5
150	1.7	2.2		0.35	0.6		5	6.1	7.5

Table 7-2 CMOS Timings at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS)	TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
	SETUP TIME (ns)			HOLD TIME (ns)			t_PDI, CLOCK PROPAGATION DELAY (ns)
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
65	6.1	7.2		6.7	7.1		4.5	6.4	8.5
80	4.7	5.8		5.3	5.8		4.5	6.4	8.5
105	3.4	4.3		3.8	4.3		4.5	6.4	8.5
125	2.7	3.6		3.1	3.6		4.5	6.4	8.5
150	1.9	2.8		2.5	2.9		4.5	6.4	8.5

Table 7-3 High-Performance Modes

PARAMETER⁽¹⁾⁽²⁾	DESCRIPTION
High-performance mode	Set the HIGH PERF MODE register bit to obtain best performance across sample clock and input signal frequencies. See Figure 7-5. Register address = 03h, data = 03h
High-frequency mode	Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input signal frequencies greater than 200 MHz. See Figure 7-5. Register address = 4Ah, data = 01h Register address = 58h, data = 01h

(1) It is recommended to use these modes to obtain best performance.

(2) See the Serial Interface Configuration section for details on register programming.

A. Dn = bits D0, D1, D2, etc. of channels A and B.

Figure 7-1 CMOS Interface Timing Diagram

A. ADC latency after reset. At higher sampling frequencies, t_PDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1.

B. E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.).

Figure 7-2 Latency Timing Diagram

Figure 7-3 ADS4246/45/42 LVDS Interface Timing Diagram

Figure 7-4 ADS4226/25/22 LVDS Interface Timing Diagram

A. With external 100-Ω termination.

Figure 7-5 LVDS Output Voltage Levels