At T_A = 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 7-28 FFT for 20-MHz Input Signal

Figure 7-30 FFT for 300-MHz Input Signal

Figure 7-32 FFT for Two-Tone Input Signal

Figure 7-34 SNR vs Input Frequency (CMOS)

Figure 7-36 SINAD vs Gain and Input Frequency

Figure 7-38 Performance vs Input Amplitude

Figure 7-40 Performance vs Input Common-Mode Voltage

Figure 7-42 SNR vs Temperature and AVDD Supply

Figure 7-44 Performance vs Input Clock Amplitude

Figure 7-46 Integrated Nonlinearity

Figure 7-29 FFT for 170-MHz Input Signal

Figure 7-31 FFT for Two-Tone Input Signal

Figure 7-33 SNR vs Input Frequency

Figure 7-35 SFDR vs Gain and Input Frequency

Figure 7-37 Performance vs Input Amplitude

Figure 7-39 Performance vs Input Common-Mode Voltage

Figure 7-41 SFDR vs Temperature and AVDD Supply

Figure 7-43 Performance vs DRVDD Supply Voltage

Figure 7-45 Performance vs Input Clock Duty Cycle

Figure 7-47 Output Noise Histogram (With Inputs Shorted to VCM)