All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5V_PP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 6-33 Spurious-Free Dynamic Range (0dB Gain)

Figure 6-35 Signal-To-Noise Ratio (0dB Gain)

Figure 6-37 Signal-To-Noise Ratio (0dB Gain)

Figure 6-34 Spurious-Free Dynamic Range (6dB Gain)

Figure 6-36 Signal-To-Noise Ratio (6dB Gain)

Figure 6-38 Signal-To-Noise Ratio (6dB Gain)